src/soc/mediatek/common/wdt.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <console/console.h>
   5 #include <soc/wdt.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 __weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ }
   9
  10 int mtk_wdt_init(void)
  11 {
  12         uint32_t wdt_sta;
  13
  14         /* Writing mode register will clear status register */
  15         wdt_sta = read32(&mtk_wdt->wdt_status);
  16
  17         mtk_wdt_clr_status(wdt_sta);
  18
  19         printk(BIOS_INFO, "WDT: Status = %#x\n", wdt_sta);
  20
  21         printk(BIOS_INFO, "WDT: Last reset was ");
  22         if (wdt_sta & MTK_WDT_STA_HW_RST) {
  23                 printk(BIOS_INFO, "hardware watchdog\n");
  24                 mark_watchdog_tombstone();
  25
  26                 /*
  27                  * We trigger secondary reset by triggering WDT hardware to send signal to EC.
  28                  * We do not use do_board_reset() to send signal to EC
  29                  * which is controlled by software driver.
  30                  */
  31                 write32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
  32                 write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
  33         } else if (wdt_sta & MTK_WDT_STA_SW_RST)
  34                 printk(BIOS_INFO, "normal software reboot\n");
  35         else if (wdt_sta & MTK_WDT_STA_SPM_RST)
  36                 printk(BIOS_INFO, "SPM reboot\n");
  37         else if (!wdt_sta)
  38                 printk(BIOS_INFO, "cold boot\n");
  39         else
  40                 printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta);
  41
  42         /* Config watchdog reboot mode:
  43          * Clearing bits:
  44          * DUAL_MODE & IRQ: trigger reset instead of irq then reset.
  45          * EXT_POL: select watchdog output signal as active low.
  46          * ENABLE: disable watchdog on initialization.
  47          * Setting bit EXTEN to enable watchdog output.
  48          */
  49         clrsetbits32(&mtk_wdt->wdt_mode,
  50                      MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
  51                      MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
  52                      MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
  53
  54         return wdt_sta;
  55 }