src/mainboard/google/brya/variants/gimble4es/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> NC */
  13         PAD_NC(GPP_A7, NONE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A12 : SATAXPCIE1 ==>  NC  */
  17         PAD_NC(GPP_A12, NONE),
  18         /* A14 : USB_OC1# ==> NC */
  19         PAD_NC(GPP_A14, NONE),
  20         /* A15 : USB_OC2# ==> NC */
  21         PAD_NC(GPP_A15, NONE),
  22         /* A18 : DDSP_HPDB ==> NC */
  23         PAD_NC(GPP_A18, NONE),
  24         /* A21 : DDPC_CTRCLK ==> NC */
  25         PAD_NC(GPP_A21, NONE),
  26         /* A22 : DDPC_CTRLDATA ==> NC */
  27         PAD_NC(GPP_A22, NONE),
  28
  29         /* B3  : PROC_GP2 ==> NC */
  30         PAD_NC(GPP_B3, NONE),
  31         /* B5  : ISH_I2C0_SDA ==> NC */
  32         PAD_NC(GPP_B5, NONE),
  33         /* B6  : ISH_I2C0_SCL ==> NC */
  34         PAD_NC(GPP_B6, NONE),
  35
  36         /* C3 : SML0CLK ==> NC */
  37         PAD_NC(GPP_C3, NONE),
  38         /* C4 : SML0DATA ==> NC */
  39         PAD_NC(GPP_C4, NONE),
  40
  41         /* D3  : ISH_GP3 ==> NC */
  42         PAD_NC(GPP_D3, NONE),
  43         /* D5  : SRCCLKREQ0# ==> NC */
  44         PAD_NC(GPP_D5, NONE),
  45         /* D9  : ISH_SPI_CS# ==> NC */
  46         PAD_NC(GPP_D9, NONE),
  47         /* D15 : ISH_UART0_RTS# ==> NC */
  48         PAD_NC(GPP_D15, NONE),
  49         /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
  50         PAD_CFG_GPO(GPP_D16, 1, DEEP),
  51         /* D17 : UART1_RXD ==> NC */
  52         PAD_NC(GPP_D17, NONE),
  53
  54         /* E0  : SATAXPCIE0 ==> NC */
  55         PAD_NC(GPP_E0, NONE),
  56         /* E3  : PROC_GP0 ==> NC */
  57         PAD_NC(GPP_E3, NONE),
  58         /* E4  : SATA_DEVSLP0 ==> NC */
  59         PAD_NC(GPP_E4, NONE),
  60         /* E7  : PROC_GP1 ==> NC */
  61         PAD_NC(GPP_E7, NONE),
  62         /* E10 : THC0_SPI1_CS# ==> NC */
  63         PAD_NC(GPP_E10, NONE),
  64         /* E16 : RSVD_TP ==> NC */
  65         PAD_NC(GPP_E16, NONE),
  66         /* E17 : THC0_SPI1_INT# ==> NC */
  67         PAD_NC(GPP_E17, NONE),
  68         /* E18 : DDP1_CTRLCLK ==> NC */
  69         PAD_NC(GPP_E18, NONE),
  70         /* E20 : DDP2_CTRLCLK ==> NC */
  71         PAD_NC(GPP_E20, NONE),
  72
  73         /* F6  : CNV_PA_BLANKING ==> NC */
  74         PAD_NC(GPP_F6, NONE),
  75         /* F19 : SRCCLKREQ6# ==> NC */
  76         PAD_NC(GPP_F19, NONE),
  77         /* F20 : EXT_PWR_GATE# ==> NC */
  78         PAD_NC(GPP_F20, NONE),
  79         /* F21 : EXT_PWR_GATE2# ==> NC */
  80         PAD_NC(GPP_F21, NONE),
  81
  82         /* H8  : I2C4_SDA ==> NC */
  83         PAD_NC(GPP_H8, NONE),
  84         /* H9  : I2C4_SCL ==> NC */
  85         PAD_NC(GPP_H9, NONE),
  86         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
  87         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  88         /* H15 : DDPB_CTRLCLK ==> NC */
  89         PAD_NC(GPP_H15, NONE),
  90         /* H17 : DDPB_CTRLDATA ==> NC*/
  91         PAD_NC(GPP_H17, NONE),
  92         /* H19 : SRCCLKREQ4# ==> NC */
  93         PAD_NC(GPP_H19, NONE),
  94         /* H21 : IMGCLKOUT2 ==> NC */
  95         PAD_NC(GPP_H21, NONE),
  96         /* H22 : IMGCLKOUT3 ==> NC */
  97         PAD_NC(GPP_H22, NONE),
  98         /* H23 : SRCCLKREQ5# ==> NC */
  99         PAD_NC(GPP_H23, NONE),
 100
 101         /* S4 : SNDW2_CLK ==> NC */
 102         PAD_NC(GPP_S4, NONE),
 103         /* S5 : SNDW2_DATA ==> NC */
 104         PAD_NC(GPP_S5, NONE),
 105         /* S6 : SNDW3_CLK ==> NC */
 106         PAD_NC(GPP_S6, NONE),
 107         /* S7 : SNDW3_DATA ==> NC */
 108         PAD_NC(GPP_S7, NONE),
 109
 110         /* GPD11: LANPHYC ==> NC */
 111         PAD_NC(GPD11, NONE),
 112 };
 113
 114 /* Early pad configuration in bootblock */
 115 static const struct pad_config early_gpio_table[] = {
 116         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 117         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 118
 119         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 120         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 121         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 122         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 123         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
 124         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
 125         /*
 126          * D1  : ISH_GP1 ==> FP_RST_ODL
 127          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 128          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 129          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 130          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 131          * FPMCU not working after a S3 resume. This is a known issue.
 132          */
 133         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 134         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 135         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 136         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 137         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 138
 139         /* E0  : SATAXPCIE0 ==> NC */
 140         PAD_NC(GPP_E0, NONE),
 141         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 142         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 143         /* E15 : RSVD_TP ==> PCH_WP_OD */
 144         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 145         /* E16 : RSVD_TP ==> NC */
 146         PAD_NC(GPP_E16, NONE),
 147         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 148         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 149         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 150         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 151         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 152         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 153         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 154         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 155 };
 156
 157 static const struct pad_config romstage_gpio_table[] = {
 158         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 159         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 160         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 161         PAD_CFG_GPO(GPP_D18, 1, DEEP),
 162 };
 163
 164 const struct pad_config *variant_gpio_override_table(size_t *num)
 165 {
 166         *num = ARRAY_SIZE(override_gpio_table);
 167         return override_gpio_table;
 168 }
 169
 170 const struct pad_config *variant_early_gpio_table(size_t *num)
 171 {
 172         *num = ARRAY_SIZE(early_gpio_table);
 173         return early_gpio_table;
 174 }
 175
 176 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 177 {
 178         *num = ARRAY_SIZE(romstage_gpio_table);
 179         return romstage_gpio_table;
 180 }