soc/intel/skylake: Correct address of I2C5 Device
[coreboot.git] / src / lib / romstage_stack.c
blobfde9d1b9b2da29e2a838ab4123e0557b47655ae9
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015-2016 Intel Corp.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <program_loading.h>
18 #include <cbmem.h>
21 * Romstage needs quite a bit of stack for decompressing images since the lzma
22 * lib keeps its state on the stack during romstage.
24 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
26 uintptr_t romstage_ram_stack_base(size_t size, int src)
28 /* cbmem_add() does a find() before add(). */
29 if (src == ROMSTAGE_STACK_CBMEM)
30 return (uintptr_t)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, size);
31 if (src == ROMSTAGE_STACK_LOW_MEM)
32 return CONFIG_RAMTOP - size;
33 return 0;
36 uintptr_t romstage_ram_stack_bottom(void)
38 return romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
39 ROMSTAGE_STACK_CBMEM);
42 uintptr_t romstage_ram_stack_top(void)
44 uintptr_t stack_top = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
45 ROMSTAGE_STACK_CBMEM);
46 stack_top += ROMSTAGE_RAM_STACK_SIZE;
47 return stack_top;