soc/intel/skylake: Correct address of I2C5 Device
[coreboot.git] / src / lib / ramtest.c
bloba29fa25ece2bb7bcaf2dbd1fc8c23a7077023c0e
1 #include <stdint.h>
2 #include <lib.h> /* Prototypes */
3 #include <console/console.h>
5 static void write_phys(unsigned long addr, u32 value)
7 // Assembler in lib/ is very ugly. But we properly guarded
8 // it so let's obey this one for now
9 #if CONFIG_SSE2
10 asm volatile(
11 "movnti %1, (%0)"
12 : /* outputs */
13 : "r" (addr), "r" (value) /* inputs */
14 #ifndef __GNUC__ /* GCC does not like empty clobbers? */
15 : /* clobbers */
16 #endif
18 #else
19 volatile unsigned long *ptr;
20 ptr = (void *)addr;
21 *ptr = value;
22 #endif
25 static u32 read_phys(unsigned long addr)
27 volatile unsigned long *ptr;
28 ptr = (void *)addr;
29 return *ptr;
32 static void phys_memory_barrier(void)
34 #if CONFIG_SSE2
35 // Needed for movnti
36 asm volatile (
37 "sfence"
39 #ifdef __GNUC__ /* ROMCC does not like memory clobbers */
40 : "memory"
41 #endif
43 #else
44 #ifdef __GNUC__ /* ROMCC does not like empty asm statements */
45 asm volatile ("" ::: "memory");
46 #endif
47 #endif
50 /**
51 * Rotate ones test pattern that access every bit on a 128bit wide
52 * memory bus. To test most address lines, addresses are scattered
53 * using 256B, 4kB and 64kB increments.
55 * @param idx Index to test pattern (0=<idx<0x400)
56 * @param addr Memory to access on idx
57 * @param value Value to write or read at addr
59 static inline void test_pattern(unsigned short int idx,
60 unsigned long *addr, unsigned long *value)
62 uint8_t j, k;
64 k = (idx >> 8) + 1;
65 j = (idx >> 4) & 0x0f;
66 *addr = idx & 0x0f;
67 *addr |= j << (4*k);
68 *value = 0x01010101 << (j & 7);
69 if (j & 8)
70 *value = ~(*value);
73 /**
74 * Simple write-read-verify memory test. See console debug output for
75 * any dislocated bytes.
77 * @param start System memory offset, aligned to 128bytes
79 static int ram_bitset_nodie(unsigned long start)
81 unsigned long addr, value, value2;
82 unsigned short int idx;
83 unsigned char failed, failures;
84 uint8_t verbose = 0;
86 printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start);
87 for (idx=0; idx<0x400; idx+=4) {
88 test_pattern(idx, &addr, &value);
89 write_phys(start + addr, value);
92 /* Make sure we don't read before we wrote */
93 phys_memory_barrier();
95 printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start);
96 failures = 0;
97 for (idx=0; idx<0x400; idx+=4) {
98 test_pattern(idx, &addr, &value);
99 value2 = read_phys(start + addr);
101 failed = (value2 != value);
102 failures |= failed;
103 if (failed && !verbose) {
104 printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx FAIL\n",
105 start + addr, value, value2);
107 if (verbose) {
108 if ((addr & 0x0f) == 0)
109 printk(BIOS_DEBUG, "%08lx wr: %08lx rd:",
110 start + addr, value);
111 if (failed)
112 printk(BIOS_DEBUG, " %08lx!", value2);
113 else
114 printk(BIOS_DEBUG, " %08lx ", value2);
115 if ((addr & 0x0f) == 0xc)
116 printk(BIOS_DEBUG, "\n");
119 if (failures) {
120 post_code(0xea);
121 printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
122 return 1;
123 } else {
124 printk(BIOS_DEBUG, "\nDRAM range verified.\n");
126 return 0;
130 void ram_check(unsigned long start, unsigned long stop)
133 * This is much more of a "Is my DRAM properly configured?"
134 * test than a "Is my DRAM faulty?" test. Not all bits
135 * are tested. -Tyson
137 printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start);
138 if (ram_bitset_nodie(start))
139 die("DRAM ERROR");
140 printk(BIOS_DEBUG, "Done.\n");
144 int ram_check_nodie(unsigned long start, unsigned long stop)
146 int ret;
148 * This is much more of a "Is my DRAM properly configured?"
149 * test than a "Is my DRAM faulty?" test. Not all bits
150 * are tested. -Tyson
152 printk(BIOS_DEBUG, "Testing DRAM at : %08lx\n", start);
154 ret = ram_bitset_nodie(start);
155 printk(BIOS_DEBUG, "Done.\n");
156 return ret;
159 int ram_check_noprint_nodie(unsigned long start, unsigned long stop)
161 unsigned long addr, value, value2;
162 unsigned short int idx;
163 unsigned char failed, failures;
165 for (idx=0; idx<0x400; idx+=4) {
166 test_pattern(idx, &addr, &value);
167 write_phys(start + addr, value);
170 /* Make sure we don't read before we wrote */
171 phys_memory_barrier();
173 failures = 0;
174 for (idx=0; idx<0x400; idx+=4) {
175 test_pattern(idx, &addr, &value);
176 value2 = read_phys(start + addr);
178 failed = (value2 != value);
179 failures |= failed;
181 return failures;
184 void quick_ram_check(void)
186 int fail = 0;
187 u32 backup;
188 backup = read_phys(CONFIG_RAMBASE);
189 write_phys(CONFIG_RAMBASE, 0x55555555);
190 phys_memory_barrier();
191 if (read_phys(CONFIG_RAMBASE) != 0x55555555)
192 fail=1;
193 write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
194 phys_memory_barrier();
195 if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
196 fail=1;
197 write_phys(CONFIG_RAMBASE, 0x00000000);
198 phys_memory_barrier();
199 if (read_phys(CONFIG_RAMBASE) != 0x00000000)
200 fail=1;
201 write_phys(CONFIG_RAMBASE, 0xffffffff);
202 phys_memory_barrier();
203 if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
204 fail=1;
206 write_phys(CONFIG_RAMBASE, backup);
207 if (fail) {
208 post_code(0xea);
209 die("RAM INIT FAILURE!\n");
211 phys_memory_barrier();