src/soc/intel/skylake/bootblock/pch.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Google Inc.
   5  * Copyright (C) 2015 Intel Corporation.
   6  * Copyright (C) 2016 Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <arch/io.h>
  18 #include <soc/bootblock.h>
  19 #include <soc/iomap.h>
  20 #include <soc/lpc.h>
  21 #include <soc/p2sb.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/pcr.h>
  24 #include <soc/spi.h>
  25
  26 /*
  27  * Enable Prefetching and Caching.
  28  */
  29 static void enable_spi_prefetch(void)
  30 {
  31         u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc);
  32         reg8 &= ~(3 << 2);
  33         reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
  34         pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
  35 }
  36
  37 static void enable_spibar(void)
  38 {
  39         device_t dev = PCH_DEV_SPI;
  40         u8 pcireg;
  41
  42         /* Assign Resources to SPI Controller */
  43         /* Clear BIT 1-2 SPI Command Register */
  44         pcireg = pci_read_config8(dev, PCI_COMMAND);
  45         pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  46         pci_write_config8(dev, PCI_COMMAND, pcireg);
  47
  48         /* Program Temporary BAR for SPI */
  49         pci_write_config32(dev, PCI_BASE_ADDRESS_0,
  50                 SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
  51
  52         /* Enable Bus Master and MMIO Space */
  53         pcireg = pci_read_config8(dev, PCI_COMMAND);
  54         pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  55         pci_write_config8(dev, PCI_COMMAND, pcireg);
  56 }
  57
  58 static void enable_p2sbbar(void)
  59 {
  60         device_t dev = PCH_DEV_P2SB;
  61
  62         /* Enable PCR Base address in PCH */
  63         pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS);
  64
  65         /* Enable P2SB MSE */
  66         pci_write_config8(dev, PCI_COMMAND,
  67                           PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  68
  69         /*
  70          * Enable decoding for HPET memory address range.
  71          * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
  72          * the High Performance Timer memory address range
  73          * selected by bits 1:0
  74          */
  75         pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
  76 }
  77
  78 void bootblock_pch_early_init(void)
  79 {
  80         enable_spibar();
  81         enable_spi_prefetch();
  82         enable_p2sbbar();
  83 }