1 ## SPDX-License-Identifier: GPL-2.0-only
3 mainmenu "coreboot configuration"
12 string "Local version string"
14 Append an extra string to the end of the coreboot version.
16 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
21 config CONFIGURABLE_CBFS_PREFIX
24 Select this to prompt to use to configure the prefix for cbfs files.
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
31 config CBFS_PREFIX_FALLBACK
34 config CBFS_PREFIX_NORMAL
37 config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
43 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
51 prompt "Compiler to use"
54 This option allows you to select the compiler used for building
56 You must build the coreboot crosscompiler for the board that you
59 To build all the GCC crosscompilers (takes a LONG time), run:
62 For help on individual architectures, run the command:
68 Use the GNU Compiler Collection (GCC) to build coreboot.
70 For details see http://gcc.gnu.org.
72 config COMPILER_LLVM_CLANG
74 depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG
76 Use LLVM/clang to build coreboot. To use this, you must build the
77 coreboot version of the clang compiler. Run the command
79 Note that Clang is not currently working on all architectures.
81 For details see http://clang.llvm.org.
85 config ARCH_SUPPORTS_CLANG
88 Opt-in flag for architectures that generally work well with CLANG.
89 By default the option would be hidden.
91 config ALLOW_EXPERIMENTAL_CLANG
92 bool "Allow experimental LLVM/Clang"
93 depends on !ARCH_SUPPORTS_CLANG
95 On some architectures CLANG does not work that well.
96 Use this only to try to get CLANG working.
99 bool "Allow building with any toolchain"
102 Many toolchains break when building coreboot since it uses quite
103 unusual linker features. Unless developers explicitly request it,
104 we'll have to assume that they use their distro compiler by mistake.
105 Make sure that using patched compilers is a conscious decision.
108 bool "Use ccache to speed up (re)compilation"
111 Enables the use of ccache for faster builds.
113 Requires the ccache utility in your system $PATH.
115 For details see https://ccache.samba.org.
118 bool "Generate flashmap descriptor parser using flex and bison"
121 Enable this option if you are working on the flashmap descriptor
122 parser and made changes to fmd_scanner.l or fmd_parser.y.
124 Otherwise, say N to use the provided pregenerated scanner/parser.
126 config UTIL_GENPARSER
127 bool "Generate parsers for bincfg, sconfig and kconfig locally"
130 Enable this option if you are working on the sconfig device tree
131 parser or bincfg and made changes to the .l or .y files.
133 Otherwise, say N to use the provided pregenerated scanner/parser.
136 prompt "Option backend to use"
137 default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
138 default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
140 config OPTION_BACKEND_NONE
143 config USE_OPTION_TABLE
144 bool "Use CMOS for configuration values"
145 depends on HAVE_OPTION_TABLE
147 Enable this option if coreboot shall read options from the "CMOS"
148 NVRAM instead of using hard-coded values.
150 config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND
151 bool "Use mainboard-specific option backend"
152 depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
154 Use a mainboard-specific mechanism to access runtime-configurable
159 config STATIC_OPTION_TABLE
160 bool "Load default configuration values into CMOS on each boot"
161 depends on USE_OPTION_TABLE
163 Enable this option to reset "CMOS" NVRAM values to default on
164 every boot. Use this if you want the NVRAM configuration to
165 never be modified from its default values.
167 config COMPRESS_RAMSTAGE
168 bool "Compress ramstage with LZMA"
169 depends on HAVE_RAMSTAGE
170 # Default value set at the end of the file
172 Compress ramstage to save memory in the flash image.
174 config COMPRESS_PRERAM_STAGES
175 bool "Compress romstage and verstage with LZ4"
176 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
177 # Default value set at the end of the file
179 Compress romstage and (if it exists) verstage with LZ4 to save flash
180 space and speed up boot, since the time for reading the image from SPI
181 (and in the vboot case verifying it) is usually much greater than the
182 time spent decompressing. Doesn't work for XIP stages (assume all
183 ARCH_X86 for now) for obvious reasons.
185 config COMPRESS_BOOTBLOCK
187 depends on HAVE_BOOTBLOCK
189 This option can be used to compress the bootblock with LZ4 and attach
190 a small self-decompression stub to its front. This can drastically
191 reduce boot time on platforms where the bootblock is loaded over a
192 very slow connection and bootblock size trumps all other factors for
193 speed. Since using this option usually requires changes to the
194 SoC memlayout and possibly extra support code, it should not be
195 user-selectable. (There's no real point in offering this to the user
196 anyway... if it works and saves boot time, you would always want it.)
198 config INCLUDE_CONFIG_FILE
199 bool "Include the coreboot .config file into the ROM image"
200 # Default value set at the end of the file
202 Include the .config file that was used to compile coreboot
203 in the (CBFS) ROM image. This is useful if you want to know which
204 options were used to build a specific coreboot.rom image.
206 Saying Y here will increase the image size by 2-3KB.
208 You can use the following command to easily list the options:
210 grep -a CONFIG_ coreboot.rom
212 Alternatively, you can also use cbfstool to print the image
213 contents (including the raw 'config' item we're looking for).
217 $ cbfstool coreboot.rom print
218 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
222 Name Offset Type Size
223 cmos_layout.bin 0x0 CMOS layout 1159
224 fallback/romstage 0x4c0 stage 339756
225 fallback/ramstage 0x53440 stage 186664
226 fallback/payload 0x80dc0 payload 51526
227 config 0x8d740 raw 3324
228 (empty) 0x8e480 null 3610440
230 config COLLECT_TIMESTAMPS
231 bool "Create a table of timestamps collected during boot"
232 default y if ARCH_X86
234 Make coreboot create a table of timer-ID/timer-value pairs to
235 allow measuring time spent at different phases of the boot process.
237 config TIMESTAMPS_ON_CONSOLE
238 bool "Print the timestamp values on the console"
240 depends on COLLECT_TIMESTAMPS
242 Print the timestamps to the debug console if enabled at level info.
245 bool "Allow use of binary-only repository"
248 This draws in the blobs repository, which contains binary files that
249 might be required for some chipsets or boards.
250 This flag ensures that a "Free" option remains available for users.
253 bool "Allow AMD blobs repository (with license agreement)"
256 This draws in the amd_blobs repository, which contains binary files
257 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
258 etc. Selecting this item to download or clone the repo implies your
259 agreement to the AMD license agreement. A copy of the license text
260 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
261 and your copy of the license is present in the repo once downloaded.
263 Note that for some products, omitting PSP, SMU images, or other items
264 may result in a nonbooting coreboot.rom.
267 bool "Allow QC blobs repository (selecting this agrees to the license!)"
270 This draws in the qc_blobs repository, which contains binary files
271 distributed by Qualcomm that are required to build firmware for
272 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
273 firmware). If you say Y here you are implicitly agreeing to the
274 Qualcomm license agreement which can be found at:
275 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
277 *****************************************************
278 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
279 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
280 *****************************************************
282 Not selecting this option means certain Qualcomm SoCs and related
283 mainboards cannot be built and will be hidden from the "Mainboards"
287 bool "Code coverage support"
288 depends on COMPILER_GCC
290 Add code coverage support for coreboot. This will store code
291 coverage information in CBMEM for extraction from user space.
295 bool "Undefined behavior sanitizer support"
298 Instrument the code with checks for undefined behavior. If unsure,
299 say N because it adds a small performance penalty and may abort
300 on code that happens to work in spite of the UB.
302 config HAVE_ASAN_IN_ROMSTAGE
306 config ASAN_IN_ROMSTAGE
310 Enable address sanitizer in romstage for platform.
312 config HAVE_ASAN_IN_RAMSTAGE
316 config ASAN_IN_RAMSTAGE
320 Enable address sanitizer in ramstage for platform.
323 bool "Address sanitizer support"
325 select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
326 select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
327 depends on COMPILER_GCC
329 Enable address sanitizer - runtime memory debugger,
330 designed to find out-of-bounds accesses and use-after-scope bugs.
332 This feature consumes up to 1/8 of available memory and brings about
333 ~1.5x performance slowdown.
338 comment "Before using this feature, make sure that "
339 comment "asan_shadow_offset_callback patch is applied to GCC."
343 prompt "Stage Cache for ACPI S3 resume"
344 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
345 default TSEG_STAGE_CACHE if SMM_TSEG
347 config NO_STAGE_CACHE
350 Do not save any component in stage cache for resume path. On resume,
351 all components would be read back from CBFS again.
353 config TSEG_STAGE_CACHE
357 The option enables stage cache support for platform. Platform
358 can stash copies of postcar, ramstage and raw runtime data
359 inside SMM TSEG, to be restored on S3 resume path.
361 config CBMEM_STAGE_CACHE
365 The option enables stage cache support for platform. Platform
366 can stash copies of postcar, ramstage and raw runtime data
369 While the approach is faster than reloading stages from boot media
370 it is also a possible attack scenario via which OS can possibly
371 circumvent SMM locks and SPI write protections.
373 If unsure, select 'N'
378 bool "Update existing coreboot.rom image"
380 If this option is enabled, no new coreboot.rom file
381 is created. Instead it is expected that there already
382 is a suitable file for further processing.
383 The bootblock will not be modified.
385 If unsure, select 'N'
387 config BOOTSPLASH_IMAGE
388 bool "Add a bootsplash image"
390 Select this option if you have a bootsplash image that you would
391 like to add to your ROM.
393 This will only add the image to the ROM. To actually run it check
394 options under 'Display' section.
396 config BOOTSPLASH_FILE
397 string "Bootsplash path and filename"
398 depends on BOOTSPLASH_IMAGE
399 # Default value set at the end of the file
401 The path and filename of the file to use as graphical bootsplash
402 screen. The file format has to be jpg.
405 bool "Firmware Configuration Probing"
408 Enable support for probing devices with fw_config. This is a simple
409 bitmask broken into fields and options for probing.
411 config FW_CONFIG_SOURCE_CHROMEEC_CBI
412 bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
413 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
416 This option tells coreboot to read the firmware configuration value
417 from the Google Chrome Embedded Controller CBI interface. This source
418 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
421 config FW_CONFIG_SOURCE_CBFS
422 bool "Obtain Firmware Configuration value from CBFS"
426 With this option enabled coreboot will look for the 32bit firmware
427 configuration value in CBFS at the selected prefix with the file name
428 "fw_config". This option will override other sources and allow the
429 local image to preempt the mainboard selected source and can be used as
430 FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option.
432 config FW_CONFIG_SOURCE_VPD
433 bool "Obtain Firmware Configuration value from VPD"
434 depends on FW_CONFIG && VPD
437 With this option enabled coreboot will look for the 32bit firmware
438 configuration value in VPD key name "fw_config". This option will
439 override other sources and allow the local image to preempt the mainboard
440 selected source and can be used for other FW_CONFIG_SOURCEs fallback option.
442 config HAVE_RAMPAYLOAD
446 bool "Enable coreboot flow without executing ramstage"
447 default y if ARCH_X86
448 depends on HAVE_RAMPAYLOAD
450 If this option is enabled, coreboot flow will skip ramstage
451 loading and execution of ramstage to load payload.
453 Instead it is expected to load payload from postcar stage itself.
455 In this flow coreboot will perform basic x86 initialization
456 (DRAM resource allocation), MTRR programming,
457 Skip PCI enumeration logic and only allocate BAR for fixed devices
458 (bootable devices, TPM over GSPI).
460 config HAVE_CONFIGURABLE_RAMSTAGE
463 config CONFIGURABLE_RAMSTAGE
464 bool "Enable a configurable ramstage."
465 default y if ARCH_X86
466 depends on HAVE_CONFIGURABLE_RAMSTAGE
468 A configurable ramstage allows you to select which parts of the ramstage
469 to run. Currently, we can only select a minimal PCI scanning step.
470 The minimal PCI scanning will only check those parts that are enabled
471 in the devicetree.cb. By convention none of those devices should be bridges.
473 config MINIMAL_PCI_SCANNING
474 bool "Enable minimal PCI scanning"
475 depends on CONFIGURABLE_RAMSTAGE && PCI
477 If this option is enabled, coreboot will scan only PCI devices
478 marked as mandatory in devicetree.cb
483 source "src/mainboard/Kconfig"
487 default "devicetree.cb"
489 This symbol allows mainboards to select a different file under their
490 mainboard directory for the devicetree.cb file. This allows the board
491 variants that need different devicetrees to be in the same directory.
493 Examples: "devicetree.variant.cb"
494 "variant/devicetree.cb"
496 config OVERRIDE_DEVICETREE
500 This symbol allows variants to provide an override devicetree file to
501 override the registers and/or add new devices on top of the ones
502 provided by baseboard devicetree using CONFIG_DEVICETREE.
504 Examples: "devicetree.variant-override.cb"
505 "variant/devicetree-override.cb"
508 string "fmap description file in fmd format"
509 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
512 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
513 but in some cases more complex setups are required.
514 When an fmd is specified, it overrides the default format.
517 hex "Size of CBFS filesystem in ROM"
518 depends on FMDFILE = ""
519 # Default value set at the end of the file
521 This is the part of the ROM actually managed by CBFS, located at the
522 end of the ROM (passed through cbfstool -o) on x86 and at at the start
523 of the ROM (passed through cbfstool -s) everywhere else. It defaults
524 to span the whole ROM on all but Intel systems that use an Intel Firmware
525 Descriptor. It can be overridden to make coreboot live alongside other
526 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
527 binaries. This symbol should only be used to generate a default FMAP and
528 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
532 # load site-local kconfig to allow user specific defaults and overrides
533 source "site-local/Kconfig"
535 config SYSTEM_TYPE_LAPTOP
539 config SYSTEM_TYPE_TABLET
543 config SYSTEM_TYPE_DETACHABLE
547 config SYSTEM_TYPE_CONVERTIBLE
551 config CBFS_AUTOGEN_ATTRIBUTES
555 If this option is selected, every file in cbfs which has a constraint
556 regarding position or alignment will get an additional file attribute
557 which describes this constraint.
562 source "src/soc/*/*/Kconfig"
563 source "src/soc/*/*/Kconfig.common"
565 source "src/cpu/Kconfig"
566 comment "Northbridge"
567 source "src/northbridge/*/*/Kconfig"
568 source "src/northbridge/*/*/Kconfig.common"
569 comment "Southbridge"
570 source "src/southbridge/*/*/Kconfig"
571 source "src/southbridge/*/*/Kconfig.common"
573 source "src/superio/*/*/Kconfig"
574 comment "Embedded Controllers"
575 source "src/ec/acpi/Kconfig"
576 source "src/ec/*/*/Kconfig"
578 source "src/southbridge/intel/common/firmware/Kconfig"
579 source "src/vendorcode/*/Kconfig"
581 source "src/arch/*/Kconfig"
583 config CHIPSET_DEVICETREE
587 This symbol allows a chipset to provide a set of default settings in
588 a devicetree which are common to all mainboards. This may include
589 devices (including alias names), chip drivers, register settings,
590 and others. This path is relative to the src/ directory.
592 Example: "chipset.cb"
596 source "src/device/Kconfig"
598 menu "Generic Drivers"
599 source "src/drivers/*/Kconfig"
600 source "src/drivers/*/*/Kconfig"
601 source "src/drivers/*/*/*/Kconfig"
602 source "src/commonlib/storage/Kconfig"
607 source "src/security/Kconfig"
608 source "src/vendorcode/eltan/security/Kconfig"
612 source "src/acpi/Kconfig"
614 # This option is for the current boards/chipsets where SPI flash
615 # is not the boot device. Currently nearly all boards/chipsets assume
616 # SPI flash is the boot device.
617 config BOOT_DEVICE_NOT_SPI_FLASH
621 config BOOT_DEVICE_SPI_FLASH
623 default y if !BOOT_DEVICE_NOT_SPI_FLASH
626 config BOOT_DEVICE_MEMORY_MAPPED
628 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
631 Inform system if SPI is memory-mapped or not.
633 config BOOT_DEVICE_SUPPORTS_WRITES
637 Indicate that the platform has writable boot device
646 default 0x100000 if FLATTENED_DEVICE_TREE
651 default 0x2000 if ARCH_X86
658 source "src/console/Kconfig"
660 config HAVE_ACPI_RESUME
664 config DISABLE_ACPI_HIBERNATE
668 Removes S4 from the available sleepstates
670 config RESUME_PATH_SAME_AS_BOOT
672 default y if ARCH_X86
673 depends on HAVE_ACPI_RESUME
675 This option indicates that when a system resumes it takes the
676 same path as a regular boot. e.g. an x86 system runs from the
677 reset vector at 0xfffffff0 on both resume and warm/cold boot.
679 config NO_MONOTONIC_TIMER
682 config HAVE_MONOTONIC_TIMER
684 depends on !NO_MONOTONIC_TIMER
687 The board/chipset provides a monotonic timer.
689 config GENERIC_UDELAY
691 depends on HAVE_MONOTONIC_TIMER
692 default y if !ARCH_X86
694 The board/chipset uses a generic udelay function utilizing the
699 depends on HAVE_MONOTONIC_TIMER
701 Provide a timer queue for performing time-based callbacks.
703 config COOP_MULTITASKING
706 depends on ARCH_X86 && CPU_INFO_V2
708 Cooperative multitasking allows callbacks to be multiplexed on the
709 main thread. With this enabled it allows for multiple execution paths
710 to take place when they have udelay() calls within their code.
715 depends on COOP_MULTITASKING
717 How many execution threads to cooperatively multitask with.
719 config HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
722 Selected by mainboards which implement a mainboard-specific mechanism
723 to access the values for runtime-configurable options. For example, a
724 custom BMC interface or an EEPROM with an externally-imposed layout.
726 config HAVE_OPTION_TABLE
730 This variable specifies whether a given board has a cmos.layout
731 file containing NVRAM/CMOS bit definitions.
732 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
734 config CMOS_LAYOUT_FILE
736 default "src/mainboard/\$(MAINBOARDDIR)/cmos.layout"
737 depends on HAVE_OPTION_TABLE
739 config PCI_IO_CFG_EXT
748 config USE_WATCHDOG_ON_BOOT
756 Enable Unified Memory Architecture for graphics.
761 This variable specifies whether a given board has MP table support.
762 It is usually set in mainboard/*/Kconfig.
763 Whether or not the MP table is actually generated by coreboot
764 is configurable by the user via GENERATE_MP_TABLE.
766 config HAVE_PIRQ_TABLE
769 This variable specifies whether a given board has PIRQ table support.
770 It is usually set in mainboard/*/Kconfig.
771 Whether or not the PIRQ table is actually generated by coreboot
772 is configurable by the user via GENERATE_PIRQ_TABLE.
778 Build support for NHLT (non HD Audio) ACPI table generation.
780 #These Options are here to avoid "undefined" warnings.
781 #The actual selection and help texts are in the following menu.
785 config GENERATE_MP_TABLE
786 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
788 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
790 Generate an MP table (conforming to the Intel MultiProcessor
791 specification 1.4) for this board.
795 config GENERATE_PIRQ_TABLE
796 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
798 default HAVE_PIRQ_TABLE
800 Generate a PIRQ table for this board.
804 config GENERATE_SMBIOS_TABLES
806 bool "Generate SMBIOS tables"
809 Generate SMBIOS tables for this board.
813 config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
817 If enabled, only generate SMBIOS Type 41 entries for PCI devices in
818 the devicetree for which Type 41 information is provided, e.g. with
819 the `smbios_dev_info` devicetree syntax. This is useful to manually
820 assign specific instance IDs to onboard devices irrespective of the
821 device traversal order. It is assumed that instance IDs for devices
822 of the same class are unique.
823 When disabled, coreboot autogenerates SMBIOS Type 41 entries for all
824 appropriate PCI devices in the devicetree. Instance IDs are assigned
825 successive numbers from a monotonically increasing counter, with one
826 counter for each device class.
828 config SMBIOS_PROVIDED_BY_MOBO
832 config MAINBOARD_SERIAL_NUMBER
833 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
835 depends on GENERATE_SMBIOS_TABLES
838 The Serial Number to store in SMBIOS structures.
840 config MAINBOARD_VERSION
841 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
843 depends on GENERATE_SMBIOS_TABLES
846 The Version Number to store in SMBIOS structures.
848 config MAINBOARD_SMBIOS_MANUFACTURER
849 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
851 depends on GENERATE_SMBIOS_TABLES
852 default MAINBOARD_VENDOR
854 Override the default Manufacturer stored in SMBIOS structures.
856 config MAINBOARD_SMBIOS_PRODUCT_NAME
857 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
859 depends on GENERATE_SMBIOS_TABLES
860 default MAINBOARD_PART_NUMBER
862 Override the default Product name stored in SMBIOS structures.
864 config VPD_SMBIOS_VERSION
865 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
867 depends on VPD && GENERATE_SMBIOS_TABLES
869 Selecting this option will read firmware_version from
870 VPD_RO and override SMBIOS type 0 version. One special
871 scenario of using this feature is to assign a BIOS version
872 to a coreboot image without the need to rebuild from source.
876 source "payloads/Kconfig"
880 comment "CPU Debug Settings"
881 source "src/cpu/*/Kconfig.debug_cpu"
883 comment "BLOB Debug Settings"
884 source "src/drivers/intel/fsp*/Kconfig.debug_blob"
886 comment "General Debug Settings"
888 # TODO: Better help text and detailed instructions.
890 bool "GDB debugging support"
892 depends on DRIVERS_UART
894 If enabled, you will be able to set breakpoints for gdb debugging.
895 See src/arch/x86/c_start.S for details.
898 bool "Wait for a GDB connection in the ramstage"
902 If enabled, coreboot will wait for a GDB connection in the ramstage.
906 bool "Halt when hitting a BUG() or assertion error"
909 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
911 config HAVE_DEBUG_GPIO
915 bool "Output verbose GPIO debug messages"
916 depends on HAVE_DEBUG_GPIO
919 bool "Output verbose CBFS debug messages"
922 This option enables additional CBFS related debug messages.
924 config HAVE_DEBUG_RAM_SETUP
927 config DEBUG_RAM_SETUP
928 bool "Output verbose RAM init debug messages"
930 depends on HAVE_DEBUG_RAM_SETUP
932 This option enables additional RAM init related debug messages.
933 It is recommended to enable this when debugging issues on your
934 board which might be RAM init related.
936 Note: This option will increase the size of the coreboot image.
941 bool "Check PIRQ table consistency"
943 depends on GENERATE_PIRQ_TABLE
947 config HAVE_DEBUG_SMBUS
951 bool "Output verbose SMBus debug messages"
953 depends on HAVE_DEBUG_SMBUS
955 This option enables additional SMBus (and SPD) debug messages.
957 Note: This option will increase the size of the coreboot image.
962 bool "Output verbose SMI debug messages"
964 depends on HAVE_SMI_HANDLER
965 select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH
967 This option enables additional SMI related debug messages.
969 Note: This option will increase the size of the coreboot image.
973 config DEBUG_PERIODIC_SMI
974 bool "Trigger SMI periodically"
977 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
978 # printk(BIOS_DEBUG, ...) calls.
980 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
984 This option enables additional malloc related debug messages.
986 Note: This option will increase the size of the coreboot image.
990 # Only visible if DEBUG_SPEW (8) is set.
991 config DEBUG_RESOURCES
992 bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
995 This option enables additional PCI memory and IO debug messages.
996 Note: This option will increase the size of the coreboot image.
999 config DEBUG_CONSOLE_INIT
1000 bool "Debug console initialisation code"
1003 With this option printk()'s are attempted before console hardware
1004 initialisation has been completed. Your mileage may vary.
1006 Typically you will need to modify source in console_hw_init() such
1007 that a working console appears before the one you want to debug.
1011 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
1012 # printk(BIOS_DEBUG, ...) calls.
1013 config REALMODE_DEBUG
1014 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1017 depends on PCI_OPTION_ROM_RUN_REALMODE
1019 This option enables additional x86emu related debug messages.
1021 Note: This option will increase the time to emulate a ROM.
1026 bool "Output verbose x86emu debug messages"
1028 depends on PCI_OPTION_ROM_RUN_YABEL
1030 This option enables additional x86emu related debug messages.
1032 Note: This option will increase the size of the coreboot image.
1036 config X86EMU_DEBUG_JMP
1037 bool "Trace JMP/RETF"
1039 depends on X86EMU_DEBUG
1041 Print information about JMP and RETF opcodes from x86emu.
1043 Note: This option will increase the size of the coreboot image.
1047 config X86EMU_DEBUG_TRACE
1048 bool "Trace all opcodes"
1050 depends on X86EMU_DEBUG
1052 Print _all_ opcodes that are executed by x86emu.
1054 WARNING: This will produce a LOT of output and take a long time.
1056 Note: This option will increase the size of the coreboot image.
1060 config X86EMU_DEBUG_PNP
1061 bool "Log Plug&Play accesses"
1063 depends on X86EMU_DEBUG
1065 Print Plug And Play accesses made by option ROMs.
1067 Note: This option will increase the size of the coreboot image.
1071 config X86EMU_DEBUG_DISK
1074 depends on X86EMU_DEBUG
1076 Print Disk I/O related messages.
1078 Note: This option will increase the size of the coreboot image.
1082 config X86EMU_DEBUG_PMM
1085 depends on X86EMU_DEBUG
1087 Print messages related to POST Memory Manager (PMM).
1089 Note: This option will increase the size of the coreboot image.
1094 config X86EMU_DEBUG_VBE
1095 bool "Debug VESA BIOS Extensions"
1097 depends on X86EMU_DEBUG
1099 Print messages related to VESA BIOS Extension (VBE) functions.
1101 Note: This option will increase the size of the coreboot image.
1105 config X86EMU_DEBUG_INT10
1106 bool "Redirect INT10 output to console"
1108 depends on X86EMU_DEBUG
1110 Let INT10 (i.e. character output) calls print messages to debug output.
1112 Note: This option will increase the size of the coreboot image.
1116 config X86EMU_DEBUG_INTERRUPTS
1117 bool "Log intXX calls"
1119 depends on X86EMU_DEBUG
1121 Print messages related to interrupt handling.
1123 Note: This option will increase the size of the coreboot image.
1127 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1128 bool "Log special memory accesses"
1130 depends on X86EMU_DEBUG
1132 Print messages related to accesses to certain areas of the virtual
1133 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1135 Note: This option will increase the size of the coreboot image.
1139 config X86EMU_DEBUG_MEM
1140 bool "Log all memory accesses"
1142 depends on X86EMU_DEBUG
1144 Print memory accesses made by option ROM.
1145 Note: This also includes accesses to fetch instructions.
1147 Note: This option will increase the size of the coreboot image.
1151 config X86EMU_DEBUG_IO
1152 bool "Log IO accesses"
1154 depends on X86EMU_DEBUG
1156 Print I/O accesses made by option ROM.
1158 Note: This option will increase the size of the coreboot image.
1162 config X86EMU_DEBUG_TIMINGS
1163 bool "Output timing information"
1165 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
1167 Print timing information needed by i915tool.
1171 config DEBUG_SPI_FLASH
1172 bool "Output verbose SPI flash debug messages"
1174 depends on SPI_FLASH
1176 This option enables additional SPI flash related debug messages.
1179 bool "Output verbose IPMI debug messages"
1183 This option enables additional IPMI related debug messages.
1185 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1186 # Only visible with the right southbridge and loglevel.
1187 config DEBUG_INTEL_ME
1188 bool "Verbose logging for Intel Management Engine"
1191 Enable verbose logging for Intel Management Engine driver that
1192 is present on Intel 6-series chipsets.
1196 bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
1199 This option enables additional function entry and exit debug messages
1200 for select functions.
1201 Note: This option will increase the size of the coreboot image.
1204 config DEBUG_COVERAGE
1205 bool "Debug code coverage"
1209 If enabled, the code coverage hooks in coreboot will output some
1210 information about the coverage data that is dumped.
1212 config DEBUG_BOOT_STATE
1213 bool "Debug boot state machine"
1216 Control debugging of the boot state machine. When selected displays
1217 the state boundaries in ramstage.
1219 config DEBUG_ADA_CODE
1220 bool "Compile debug code in Ada sources"
1223 Add the compiler switch `-gnata` to compile code guarded by
1226 config HAVE_EM100_SUPPORT
1229 This is enabled by platforms which can support using the EM100.
1232 bool "Configure image for EM100 usage"
1233 depends on HAVE_EM100_SUPPORT
1235 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1236 over USB. However it only supports a maximum SPI clock of 20MHz and
1237 single data output. Enable this option to use a 20MHz SPI clock and
1238 disable "Dual Output Fast Read" Support.
1240 On AMD platforms this changes the SPI speed at run-time if the
1241 mainboard code supports this. On supported Intel platforms this works
1242 by changing the settings in the descriptor.bin file.
1246 ###############################################################################
1247 # Set variables with no prompt - these can be set anywhere, and putting at
1248 # the end of this file gives the most flexibility.
1250 source "src/lib/Kconfig"
1252 config WARNINGS_ARE_ERRORS
1256 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1257 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1258 # mutually exclusive. One of these options must be selected in the
1259 # mainboard Kconfig if the chipset supports enabling and disabling of
1260 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1261 # in mainboard/Kconfig to know if the button should be enabled or not.
1263 config POWER_BUTTON_DEFAULT_ENABLE
1266 Select when the board has a power button which can optionally be
1267 disabled by the user.
1269 config POWER_BUTTON_DEFAULT_DISABLE
1272 Select when the board has a power button which can optionally be
1273 enabled by the user, e.g. when the board ships with a jumper over
1274 the power switch contacts.
1276 config POWER_BUTTON_FORCE_ENABLE
1279 Select when the board requires that the power button is always
1282 config POWER_BUTTON_FORCE_DISABLE
1285 Select when the board requires that the power button is always
1286 disabled, e.g. when it has been hardwired to ground.
1288 config POWER_BUTTON_IS_OPTIONAL
1290 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1291 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1293 Internal option that controls ENABLE_POWER_BUTTON visibility.
1299 Internal option that controls whether we compile in register scripts.
1301 config MAX_REBOOT_CNT
1305 Internal option that sets the maximum number of bootblock executions allowed
1306 with the normal image enabled before assuming the normal image is defective
1307 and switching to the fallback image.
1309 config UNCOMPRESSED_RAMSTAGE
1312 config NO_XIP_EARLY_STAGES
1314 default n if ARCH_X86
1317 Identify if early stages are eXecute-In-Place(XIP).
1319 config EARLY_CBMEM_LIST
1323 Enable display of CBMEM during romstage and postcar.
1325 config RELOCATABLE_MODULES
1328 If RELOCATABLE_MODULES is selected then support is enabled for
1329 building relocatable modules in the RAM stage. Those modules can be
1330 loaded anywhere and all the relocations are handled automatically.
1332 config GENERIC_GPIO_LIB
1335 If enabled, compile the generic GPIO library. A "generic" GPIO
1336 implies configurability usually found on SoCs, particularly the
1337 ability to control internal pull resistors.
1339 config BOOTBLOCK_CUSTOM
1340 # To be selected by arch, SoC or mainboard if it does not want use the normal
1341 # src/lib/bootblock.c#main() C entry point.
1344 config BOOTBLOCK_IN_CBFS
1346 default y if ARCH_X86
1348 Select this on platforms that have a top aligned bootblock inside cbfs.
1350 config MEMLAYOUT_LD_FILE
1352 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
1354 This variable allows SoC/mainboard to supply in a custom linker file
1355 if required. This determines the linker file used for all the stages
1356 (bootblock, romstage, verstage, ramstage, postcar) in
1357 src/arch/${ARCH}/Makefile.inc.
1359 ###############################################################################
1360 # Set default values for symbols created before mainboards. This allows the
1361 # option to be displayed in the general menu, but the default to be loaded in
1362 # the mainboard if desired.
1363 config COMPRESS_RAMSTAGE
1364 default y if !UNCOMPRESSED_RAMSTAGE
1366 config COMPRESS_PRERAM_STAGES
1367 depends on !ARCH_X86
1370 config INCLUDE_CONFIG_FILE
1373 config BOOTSPLASH_FILE
1374 depends on BOOTSPLASH_IMAGE
1375 default "bootsplash.jpg"
1380 config HAVE_BOOTBLOCK
1384 config HAVE_VERSTAGE
1386 depends on VBOOT_SEPARATE_VERSTAGE
1389 config HAVE_ROMSTAGE
1393 config HAVE_RAMSTAGE
1395 default n if RAMPAYLOAD