src/mainboard/google/zork/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <variant/ec.h>
   4
   5 /* DefinitionBlock Statement */
   6 #include <acpi/acpi.h>
   7
   8 DefinitionBlock (
   9         "dsdt.aml",
  10         "DSDT",
  11         ACPI_DSDT_REV_2,
  12         OEM_ID,
  13         ACPI_TABLE_CREATOR,
  14         0x00010001      /* OEM Revision */
  15         )
  16 {       /* Start of ASL file */
  17         #include <acpi/dsdt_top.asl>
  18
  19         /* global NVS and variables */
  20         #include <globalnvs.asl>
  21
  22         /* PCI IRQ mapping for the Southbridge */
  23         #include <pcie.asl>
  24
  25         /* Describe the processor tree (\_PR) */
  26         #include <cpu.asl>
  27
  28         /* Contains the supported sleep states for this chipset */
  29         #include <sleepstates.asl>
  30
  31         /* Contains _SWS methods */
  32         #include <soc/amd/common/acpi/acpi_wake_source.asl>
  33
  34         /* System Bus */
  35         Scope(\_SB) { /* Start \_SB scope */
  36                 /* global utility methods expected within the \_SB scope */
  37                 #include <arch/x86/acpi/globutil.asl>
  38
  39                 /* Describe the SOC */
  40                 #include <soc.asl>
  41
  42         } /* End \_SB scope */
  43
  44         /* Thermal handler */
  45         #include <variant/acpi/thermal.asl>
  46
  47         /* Chrome OS specific */
  48         #include <vendorcode/google/chromeos/acpi/chromeos.asl>
  49
  50         /* Chrome OS Embedded Controller */
  51         Scope (\_SB.PCI0.LPCB)
  52         {
  53                 /* ACPI code for EC SuperIO functions */
  54                 #include <ec/google/chromeec/acpi/superio.asl>
  55                 /* ACPI code for EC functions */
  56                 #include <ec/google/chromeec/acpi/ec.asl>
  57         }
  58 }
  59 /* End of ASL file */