1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* DefinitionBlock Statement */
11 0x00010001 /* OEM Revision */
13 { /* Start of ASL file */
14 #include <acpi/dsdt_top.asl>
16 /* Globals for the platform */
17 #include "acpi/mainboard.asl"
19 /* Describe the USB Overcurrent pins */
20 #include "acpi/usb_oc.asl"
22 /* PCI IRQ mapping for the Southbridge */
23 #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
25 /* Describe the processor tree (\_SB) */
26 #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
28 /* Contains the supported sleep states for this chipset */
29 #include <southbridge/amd/common/acpi/sleepstates.asl>
31 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
32 #include "acpi/sleep.asl"
35 Scope(\_SB) { /* Start \_SB scope */
36 /* global utility methods expected within the \_SB scope */
37 #include <arch/x86/acpi/globutil.asl>
39 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
40 #include "acpi/routing.asl"
43 Name(_HID, EISAID("PNP0C0C"))
45 Name(_PRW, Package () {3, 0x04})
50 /* Describe the AMD Northbridge */
51 #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
53 /* Describe the AMD Fusion Controller Hub Southbridge */
54 #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
57 /* Describe PCI INT[A-H] for the Southbridge */
58 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
60 } /* End \_SB scope */
62 /* Describe SMBUS for the Southbridge */
63 #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
65 /* Define the General Purpose Events for the platform */
66 #include "acpi/gpe.asl"
68 /* Define the Thermal zones and methods for the platform */
69 #include "acpi/thermal.asl"
71 /* Define the System Indicators for the platform */
72 #include "acpi/si.asl"