1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* DefinitionBlock Statement */
11 0x00010001 /* OEM Revision */
13 { /* Start of ASL file */
14 #include <acpi/dsdt_top.asl>
16 #include "acpi/mainboard.asl"
18 #include <cpu/amd/agesa/family14/acpi/cpu.asl>
20 #include "acpi/routing.asl"
23 /* global utility methods expected within the \_SB scope */
24 #include <arch/x86/acpi/globutil.asl>
28 /* Describe the AMD Northbridge */
29 #include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
31 /* Describe the AMD Fusion Controller Hub Southbridge */
32 #include <southbridge/amd/cimx/sb800/acpi/fch.asl>
34 /* Primary (and only) IDE channel */
36 Name(_ADR, 0x00140001)
37 #include "acpi/ide.asl"
41 } /* End Scope(_SB) */
43 /* Contains the supported sleep states for this chipset */
44 #include <southbridge/amd/common/acpi/sleepstates.asl>
46 /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
47 #include "acpi/sleep.asl"
49 #include "acpi/gpe.asl"