src/southbridge/amd/agesa/hudson/hudson.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 #ifndef HUDSON_H
  21 #define HUDSON_H
  22
  23 #include <device/pci_ids.h>
  24 #include <device/device.h>
  25 #include "chip.h"
  26
  27 /* Power management index/data registers */
  28 #define BIOSRAM_INDEX   0xcd4
  29 #define BIOSRAM_DATA    0xcd5
  30 #define PM_INDEX        0xcd6
  31 #define PM_DATA         0xcd7
  32 #define PM2_INDEX       0xcd0
  33 #define PM2_DATA        0xcd1
  34
  35 #define HUDSON_ACPI_IO_BASE 0x800
  36
  37 #define ACPI_PM_EVT_BLK         (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
  38 #define ACPI_PM1_CNT_BLK        (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
  39 #define ACPI_PM_TMR_BLK         (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
  40 #define ACPI_GPE0_BLK           (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
  41 #define ACPI_CPU_CONTROL        (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
  42
  43 #define ACPI_SMI_CTL_PORT               0xb2
  44 #define ACPI_SMI_CMD_CST_CONTROL        0xde
  45 #define ACPI_SMI_CMD_PST_CONTROL        0xad
  46 #define ACPI_SMI_CMD_DISABLE            0xbe
  47 #define ACPI_SMI_CMD_ENABLE             0xef
  48 #define ACPI_SMI_CMD_S4_REQ             0xc0
  49
  50 #define REV_HUDSON_A11  0x11
  51 #define REV_HUDSON_A12  0x12
  52
  53 #define SPIROM_BASE_ADDRESS_REGISTER    0xA0
  54
  55 #ifndef __SMM__
  56
  57 void pm_write8(u8 reg, u8 value);
  58 u8 pm_read8(u8 reg);
  59 void pm_write16(u8 reg, u16 value);
  60 u16 pm_read16(u16 reg);
  61
  62 #ifdef __PRE_RAM__
  63 void hudson_lpc_port80(void);
  64 void hudson_pci_port80(void);
  65 void hudson_clk_output_48Mhz(void);
  66
  67 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
  68 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
  69
  70 int acpi_is_wakeup_early(void);
  71
  72 #else
  73 void hudson_enable(device_t dev);
  74 void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev);
  75 void s3_resume_init_data(void *FchParams);
  76
  77 #endif /* __PRE_RAM__ */
  78 #endif /* __SMM__ */
  79
  80 #endif /* HUDSON_H */