2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "coreboot configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
50 prompt "Compiler to use"
53 This option allows you to select the compiler used for building
59 Use the GNU Compiler Collection (GCC) to build coreboot.
61 For details see http://gcc.gnu.org.
63 config COMPILER_LLVM_CLANG
66 Use LLVM/clang to build coreboot.
68 For details see http://clang.llvm.org.
72 config SCANBUILD_ENABLE
73 bool "Build with scan-build for static code analysis"
76 Changes the build process to use scan-build (a utility for
77 running the clang static code analyzer from the command line).
79 Requires the scan-build utility in your system $PATH.
81 For details see http://clang-analyzer.llvm.org/scan-build.html.
83 config SCANBUILD_REPORT_LOCATION
84 string "Directory for the scan-build report(s)"
86 depends on SCANBUILD_ENABLE
88 Directory where the scan-build reports should be stored in. The
89 reports are stored in subdirectories of the form 'yyyy-mm-dd-*'
90 in the specified directory.
92 If this setting is left empty, the coreboot top-level directory
93 will be used to store the report subdirectories.
96 bool "Use ccache to speed up (re)compilation"
99 Enables the use of ccache for faster builds.
101 Requires the ccache utility in your system $PATH.
103 For details see https://ccache.samba.org.
105 config SCONFIG_GENPARSER
106 bool "Generate SCONFIG parser using flex and bison"
110 Enable this option if you are working on the sconfig device tree
111 parser and made changes to sconfig.l and sconfig.y.
115 config USE_OPTION_TABLE
116 bool "Use CMOS for configuration values"
118 depends on HAVE_OPTION_TABLE
120 Enable this option if coreboot shall read options from the "CMOS"
121 NVRAM instead of using hard-coded values.
123 config COMPRESS_RAMSTAGE
124 bool "Compress ramstage with LZMA"
127 Compress ramstage to save memory in the flash image. Note
128 that decompression might slow down booting if the boot flash
129 is connected through a slow link (i.e. SPI).
131 config INCLUDE_CONFIG_FILE
132 bool "Include the coreboot .config file into the ROM image"
135 Include the .config file that was used to compile coreboot
136 in the (CBFS) ROM image. This is useful if you want to know which
137 options were used to build a specific coreboot.rom image.
139 Saying Y here will increase the image size by 2-3kB.
141 You can use the following command to easily list the options:
143 grep -a CONFIG_ coreboot.rom
145 Alternatively, you can also use cbfstool to print the image
146 contents (including the raw 'config' item we're looking for).
150 $ cbfstool coreboot.rom print
151 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
155 Name Offset Type Size
156 cmos_layout.bin 0x0 cmos layout 1159
157 fallback/romstage 0x4c0 stage 339756
158 fallback/coreboot_ram 0x53440 stage 186664
159 fallback/payload 0x80dc0 payload 51526
160 config 0x8d740 raw 3324
161 (empty) 0x8e480 null 3610440
163 config EARLY_CBMEM_INIT
164 bool "Initialize CBMEM while in ROM stage"
167 Make coreboot initialize the cbmem structures while running in ROM
168 stage. This could be useful when the ROM stage wants to communicate
169 some, for instance, execution timestamps.
171 config COLLECT_TIMESTAMPS
172 bool "Create a table of timestamps collected during boot"
173 depends on EARLY_CBMEM_INIT
175 Make coreboot create a table of timer-ID/timer-value pairs to
176 allow measuring time spent at different phases of the boot process.
179 bool "Allow use of binary-only repository"
182 This draws in the blobs repository, which contains binary files that
183 might be required for some chipsets or boards.
184 This flag ensures that a "Free" option remains available for users.
190 This option can be configured by boards that require the blobs
191 repository for the default configuration. It will make the build
192 fail if USE_BLOBS is disabled. Users that still desire to do a
193 coreboot build for such a board can override this manually, but
194 this option serves as warning that it might fail.
198 source src/mainboard/Kconfig
200 # This option is used to set the architecture of a mainboard to X86.
201 # It is usually set in mainboard/*/Kconfig.
207 source src/arch/x86/Kconfig
213 source src/cpu/Kconfig
214 comment "Northbridge"
215 source src/northbridge/Kconfig
216 comment "Southbridge"
217 source src/southbridge/Kconfig
219 source src/superio/Kconfig
221 source src/devices/Kconfig
222 comment "Embedded Controllers"
223 source src/ec/Kconfig
227 menu "Generic Drivers"
228 source src/drivers/Kconfig
231 config PCI_BUS_SEGN_BITS
247 config MMCONF_SUPPORT_DEFAULT
251 config MMCONF_SUPPORT
255 source src/console/Kconfig
257 # This should default to N and be set by SuperI/O drivers that have an UART
258 config HAVE_UART_IO_MAPPED
262 config HAVE_UART_MEMORY_MAPPED
266 config HAVE_ACPI_RESUME
270 config HAVE_ACPI_SLIC
274 config ACPI_SSDTX_NUM
278 config HAVE_HARD_RESET
280 default y if BOARD_HAS_HARD_RESET
283 This variable specifies whether a given board has a hard_reset
284 function, no matter if it's provided by board code or chipset code.
286 config HAVE_INIT_TIMER
288 default n if UDELAY_IO
291 config HIGH_SCRATCH_MEMORY_SIZE
295 config USE_OPTION_TABLE
299 config HAVE_OPTION_TABLE
303 This variable specifies whether a given board has a cmos.layout
304 file containing NVRAM/CMOS bit definitions.
305 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
311 config HAVE_SMI_HANDLER
315 config PCI_IO_CFG_EXT
327 # TODO: Can probably be removed once all chipsets have kconfig options for it.
332 config USE_WATCHDOG_ON_BOOT
340 Build board-specific VGA code.
346 Enable Unified Memory Architecture for graphics.
353 config HAVE_ACPI_TABLES
356 This variable specifies whether a given board has ACPI table support.
357 It is usually set in mainboard/*/Kconfig.
358 Whether or not the ACPI tables are actually generated by coreboot
359 is configurable by the user via GENERATE_ACPI_TABLES.
364 This variable specifies whether a given board has MP table support.
365 It is usually set in mainboard/*/Kconfig.
366 Whether or not the MP table is actually generated by coreboot
367 is configurable by the user via GENERATE_MP_TABLE.
369 config HAVE_PIRQ_TABLE
372 This variable specifies whether a given board has PIRQ table support.
373 It is usually set in mainboard/*/Kconfig.
374 Whether or not the PIRQ table is actually generated by coreboot
375 is configurable by the user via GENERATE_PIRQ_TABLE.
377 #These Options are here to avoid "undefined" warnings.
378 #The actual selection and help texts are in the following menu.
380 config GENERATE_ACPI_TABLES
382 default HAVE_ACPI_TABLES
384 config GENERATE_MP_TABLE
386 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
388 config GENERATE_PIRQ_TABLE
390 default HAVE_PIRQ_TABLE
392 config GENERATE_SMBIOS_TABLES
398 config WRITE_HIGH_TABLES
399 bool "Write 'high' tables to avoid being overwritten in F segment"
403 bool "Generate Multiboot tables (for GRUB2)"
406 config GENERATE_ACPI_TABLES
407 depends on HAVE_ACPI_TABLES
408 bool "Generate ACPI tables"
411 Generate ACPI tables for this board.
415 config GENERATE_MP_TABLE
416 depends on HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
417 bool "Generate an MP table"
420 Generate an MP table (conforming to the Intel MultiProcessor
421 specification 1.4) for this board.
425 config GENERATE_PIRQ_TABLE
426 depends on HAVE_PIRQ_TABLE
427 bool "Generate a PIRQ table"
430 Generate a PIRQ table for this board.
434 config GENERATE_SMBIOS_TABLES
436 bool "Generate SMBIOS tables"
439 Generate SMBIOS tables for this board.
448 prompt "Add a payload"
449 default PAYLOAD_NONE if !ARCH_X86
450 default PAYLOAD_SEABIOS if ARCH_X86
455 Select this option if you want to create an "empty" coreboot
456 ROM image for a certain mainboard, i.e. a coreboot ROM image
457 which does not yet contain a payload.
459 For such an image to be useful, you have to use 'cbfstool'
460 to add a payload to the ROM image later.
463 bool "An ELF executable payload"
465 Select this option if you have a payload image (an ELF file)
466 which coreboot should run as soon as the basic hardware
467 initialization is completed.
469 You will be able to specify the location and file name of the
472 config PAYLOAD_SEABIOS
476 Select this option if you want to build a coreboot image
477 with a SeaBIOS payload. If you don't know what this is
478 about, just leave it enabled.
480 See http://coreboot.org/Payloads for more information.
485 Select this option if you want to build a coreboot image
486 with a FILO payload. If you don't know what this is
487 about, just leave it enabled.
489 See http://coreboot.org/Payloads for more information.
494 prompt "SeaBIOS version"
495 default SEABIOS_STABLE
496 depends on PAYLOAD_SEABIOS
498 config SEABIOS_STABLE
501 Stable SeaBIOS version
502 config SEABIOS_MASTER
505 Newest SeaBIOS version
509 prompt "FILO version"
511 depends on PAYLOAD_FILO
524 string "Payload path and filename"
525 depends on PAYLOAD_ELF
526 default "payload.elf"
528 The path and filename of the ELF executable file to use as payload.
531 depends on PAYLOAD_SEABIOS
532 default "$(obj)/seabios/out/bios.bin.elf"
535 depends on PAYLOAD_FILO
536 default "payloads/external/FILO/filo/build/filo.elf"
538 # TODO: Defined if no payload? Breaks build?
539 config COMPRESSED_PAYLOAD_LZMA
540 bool "Use LZMA compression for payloads"
542 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
544 In order to reduce the size payloads take up in the ROM chip
545 coreboot can compress them using the LZMA algorithm.
547 config COMPRESSED_PAYLOAD_NRV2B
556 bool "Add a VGA BIOS image"
558 Select this option if you have a VGA BIOS image that you would
559 like to add to your ROM.
561 You will be able to specify the location and file name of the
565 string "VGA BIOS path and filename"
567 default "vgabios.bin"
569 The path and filename of the file to use as VGA BIOS.
572 string "VGA device PCI IDs"
576 The comma-separated PCI vendor and device ID that would associate
577 your VGA BIOS to your video card.
581 In the above example 1106 is the PCI vendor ID (in hex, but without
582 the "0x" prefix) and 3230 specifies the PCI device ID of the
583 video card (also in hex, without "0x" prefix).
586 bool "Add an MBI image"
587 depends on NORTHBRIDGE_INTEL_I82830
589 Select this option if you have an Intel MBI image that you would
590 like to add to your ROM.
592 You will be able to specify the location and file name of the
596 string "Intel MBI path and filename"
600 The path and filename of the file to use as VGA BIOS.
605 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
607 config FRAMEBUFFER_SET_VESA_MODE
608 prompt "Set VESA framebuffer mode"
610 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
612 Set VESA framebuffer mode (needed for bootsplash)
615 prompt "VESA framebuffer video mode"
616 default FRAMEBUFFER_VESA_MODE_117
617 depends on FRAMEBUFFER_SET_VESA_MODE
619 This option sets the resolution used for the coreboot framebuffer (and
622 config FRAMEBUFFER_VESA_MODE_100
623 bool "640x400 256-color"
625 config FRAMEBUFFER_VESA_MODE_101
626 bool "640x480 256-color"
628 config FRAMEBUFFER_VESA_MODE_102
629 bool "800x600 16-color"
631 config FRAMEBUFFER_VESA_MODE_103
632 bool "800x600 256-color"
634 config FRAMEBUFFER_VESA_MODE_104
635 bool "1024x768 16-color"
637 config FRAMEBUFFER_VESA_MODE_105
638 bool "1024x7686 256-color"
640 config FRAMEBUFFER_VESA_MODE_106
641 bool "1280x1024 16-color"
643 config FRAMEBUFFER_VESA_MODE_107
644 bool "1280x1024 256-color"
646 config FRAMEBUFFER_VESA_MODE_108
649 config FRAMEBUFFER_VESA_MODE_109
652 config FRAMEBUFFER_VESA_MODE_10A
655 config FRAMEBUFFER_VESA_MODE_10B
658 config FRAMEBUFFER_VESA_MODE_10C
661 config FRAMEBUFFER_VESA_MODE_10D
662 bool "320x200 32k-color (1:5:5:5)"
664 config FRAMEBUFFER_VESA_MODE_10E
665 bool "320x200 64k-color (5:6:5)"
667 config FRAMEBUFFER_VESA_MODE_10F
668 bool "320x200 16.8M-color (8:8:8)"
670 config FRAMEBUFFER_VESA_MODE_110
671 bool "640x480 32k-color (1:5:5:5)"
673 config FRAMEBUFFER_VESA_MODE_111
674 bool "640x480 64k-color (5:6:5)"
676 config FRAMEBUFFER_VESA_MODE_112
677 bool "640x480 16.8M-color (8:8:8)"
679 config FRAMEBUFFER_VESA_MODE_113
680 bool "800x600 32k-color (1:5:5:5)"
682 config FRAMEBUFFER_VESA_MODE_114
683 bool "800x600 64k-color (5:6:5)"
685 config FRAMEBUFFER_VESA_MODE_115
686 bool "800x600 16.8M-color (8:8:8)"
688 config FRAMEBUFFER_VESA_MODE_116
689 bool "1024x768 32k-color (1:5:5:5)"
691 config FRAMEBUFFER_VESA_MODE_117
692 bool "1024x768 64k-color (5:6:5)"
694 config FRAMEBUFFER_VESA_MODE_118
695 bool "1024x768 16.8M-color (8:8:8)"
697 config FRAMEBUFFER_VESA_MODE_119
698 bool "1280x1024 32k-color (1:5:5:5)"
700 config FRAMEBUFFER_VESA_MODE_11A
701 bool "1280x1024 64k-color (5:6:5)"
703 config FRAMEBUFFER_VESA_MODE_11B
704 bool "1280x1024 16.8M-color (8:8:8)"
708 # Map the config names to an integer (KB).
709 config FRAMEBUFFER_VESA_MODE
711 default 0x100 if FRAMEBUFFER_VESA_MODE_100
712 default 0x101 if FRAMEBUFFER_VESA_MODE_101
713 default 0x102 if FRAMEBUFFER_VESA_MODE_102
714 default 0x103 if FRAMEBUFFER_VESA_MODE_103
715 default 0x104 if FRAMEBUFFER_VESA_MODE_104
716 default 0x105 if FRAMEBUFFER_VESA_MODE_105
717 default 0x106 if FRAMEBUFFER_VESA_MODE_106
718 default 0x107 if FRAMEBUFFER_VESA_MODE_107
719 default 0x108 if FRAMEBUFFER_VESA_MODE_108
720 default 0x109 if FRAMEBUFFER_VESA_MODE_109
721 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
722 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
723 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
724 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
725 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
726 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
727 default 0x110 if FRAMEBUFFER_VESA_MODE_110
728 default 0x111 if FRAMEBUFFER_VESA_MODE_111
729 default 0x112 if FRAMEBUFFER_VESA_MODE_112
730 default 0x113 if FRAMEBUFFER_VESA_MODE_113
731 default 0x114 if FRAMEBUFFER_VESA_MODE_114
732 default 0x115 if FRAMEBUFFER_VESA_MODE_115
733 default 0x116 if FRAMEBUFFER_VESA_MODE_116
734 default 0x117 if FRAMEBUFFER_VESA_MODE_117
735 default 0x118 if FRAMEBUFFER_VESA_MODE_118
736 default 0x119 if FRAMEBUFFER_VESA_MODE_119
737 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
738 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
740 config FRAMEBUFFER_KEEP_VESA_MODE
741 prompt "Keep VESA framebuffer"
743 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
745 This option keeps the framebuffer mode set after coreboot finishes
746 execution. If this option is enabled, coreboot will pass a
747 framebuffer entry in its coreboot table and the payload will need a
748 framebuffer driver. If this option is disabled, coreboot will switch
749 back to text mode before handing control to a payload.
752 prompt "Show graphical bootsplash"
754 depends on FRAMEBUFFER_SET_VESA_MODE
756 This option shows a graphical bootsplash screen. The grapics are
757 loaded from the CBFS file bootsplash.jpg.
759 config BOOTSPLASH_FILE
760 string "Bootsplash path and filename"
761 depends on BOOTSPLASH
762 default "bootsplash.jpg"
764 The path and filename of the file to use as graphical bootsplash
765 screen. The file format has to be jpg.
770 # TODO: Better help text and detailed instructions.
772 bool "GDB debugging support"
775 If enabled, you will be able to set breakpoints for gdb debugging.
776 See src/arch/x86/lib/c_start.S for details.
779 bool "Wait for a GDB connection"
783 If enabled, coreboot will wait for a GDB connection.
786 bool "Output verbose CBFS debug messages"
790 This option enables additional CBFS related debug messages.
792 config HAVE_DEBUG_RAM_SETUP
795 config DEBUG_RAM_SETUP
796 bool "Output verbose RAM init debug messages"
798 depends on HAVE_DEBUG_RAM_SETUP
800 This option enables additional RAM init related debug messages.
801 It is recommended to enable this when debugging issues on your
802 board which might be RAM init related.
804 Note: This option will increase the size of the coreboot image.
808 config HAVE_DEBUG_CAR
813 depends on HAVE_DEBUG_CAR
815 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
816 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
817 # printk(BIOS_DEBUG, ...) calls.
819 bool "Output verbose Cache-as-RAM debug messages"
821 depends on HAVE_DEBUG_CAR
823 This option enables additional CAR related debug messages.
827 bool "Check PIRQ table consistency"
829 depends on GENERATE_PIRQ_TABLE
833 config HAVE_DEBUG_SMBUS
837 bool "Output verbose SMBus debug messages"
839 depends on HAVE_DEBUG_SMBUS
841 This option enables additional SMBus (and SPD) debug messages.
843 Note: This option will increase the size of the coreboot image.
848 bool "Output verbose SMI debug messages"
850 depends on HAVE_SMI_HANDLER
852 This option enables additional SMI related debug messages.
854 Note: This option will increase the size of the coreboot image.
858 config DEBUG_SMM_RELOCATION
859 bool "Debug SMM relocation code"
861 depends on HAVE_SMI_HANDLER
863 This option enables additional SMM handler relocation related
866 Note: This option will increase the size of the coreboot image.
873 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
874 # printk(BIOS_DEBUG, ...) calls.
875 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
877 bool "Output verbose malloc debug messages"
880 This option enables additional malloc related debug messages.
882 Note: This option will increase the size of the coreboot image.
890 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
891 # printk(BIOS_DEBUG, ...) calls.
892 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
894 bool "Output verbose ACPI debug messages"
897 This option enables additional ACPI related debug messages.
899 Note: This option will slightly increase the size of the coreboot image.
904 config REALMODE_DEBUG
906 depends on PCI_OPTION_ROM_RUN_REALMODE
908 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
909 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
910 # printk(BIOS_DEBUG, ...) calls.
911 config REALMODE_DEBUG
912 bool "Enable debug messages for option ROM execution"
914 depends on PCI_OPTION_ROM_RUN_REALMODE
916 This option enables additional x86emu related debug messages.
918 Note: This option will increase the time to emulate a ROM.
924 bool "Output verbose x86emu debug messages"
926 depends on PCI_OPTION_ROM_RUN_YABEL
928 This option enables additional x86emu related debug messages.
930 Note: This option will increase the size of the coreboot image.
934 config X86EMU_DEBUG_JMP
935 bool "Trace JMP/RETF"
937 depends on X86EMU_DEBUG
939 Print information about JMP and RETF opcodes from x86emu.
941 Note: This option will increase the size of the coreboot image.
945 config X86EMU_DEBUG_TRACE
946 bool "Trace all opcodes"
948 depends on X86EMU_DEBUG
950 Print _all_ opcodes that are executed by x86emu.
952 WARNING: This will produce a LOT of output and take a long time.
954 Note: This option will increase the size of the coreboot image.
958 config X86EMU_DEBUG_PNP
959 bool "Log Plug&Play accesses"
961 depends on X86EMU_DEBUG
963 Print Plug And Play accesses made by option ROMs.
965 Note: This option will increase the size of the coreboot image.
969 config X86EMU_DEBUG_DISK
972 depends on X86EMU_DEBUG
974 Print Disk I/O related messages.
976 Note: This option will increase the size of the coreboot image.
980 config X86EMU_DEBUG_PMM
983 depends on X86EMU_DEBUG
985 Print messages related to POST Memory Manager (PMM).
987 Note: This option will increase the size of the coreboot image.
992 config X86EMU_DEBUG_VBE
993 bool "Debug VESA BIOS Extensions"
995 depends on X86EMU_DEBUG
997 Print messages related to VESA BIOS Extension (VBE) functions.
999 Note: This option will increase the size of the coreboot image.
1003 config X86EMU_DEBUG_INT10
1004 bool "Redirect INT10 output to console"
1006 depends on X86EMU_DEBUG
1008 Let INT10 (i.e. character output) calls print messages to debug output.
1010 Note: This option will increase the size of the coreboot image.
1014 config X86EMU_DEBUG_INTERRUPTS
1015 bool "Log intXX calls"
1017 depends on X86EMU_DEBUG
1019 Print messages related to interrupt handling.
1021 Note: This option will increase the size of the coreboot image.
1025 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1026 bool "Log special memory accesses"
1028 depends on X86EMU_DEBUG
1030 Print messages related to accesses to certain areas of the virtual
1031 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1033 Note: This option will increase the size of the coreboot image.
1037 config X86EMU_DEBUG_MEM
1038 bool "Log all memory accesses"
1040 depends on X86EMU_DEBUG
1042 Print memory accesses made by option ROM.
1043 Note: This also includes accesses to fetch instructions.
1045 Note: This option will increase the size of the coreboot image.
1049 config X86EMU_DEBUG_IO
1050 bool "Log IO accesses"
1052 depends on X86EMU_DEBUG
1054 Print I/O accesses made by option ROM.
1056 Note: This option will increase the size of the coreboot image.
1061 bool "Output verbose TPM debug messages"
1065 This option enables additional TPM related debug messages.
1067 config DEBUG_SPI_FLASH
1068 bool "Output verbose SPI flash debug messages"
1070 depends on SPI_FLASH
1072 This option enables additional SPI flash related debug messages.
1074 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1075 # Only visible with the right southbridge and loglevel.
1076 config DEBUG_INTEL_ME
1077 bool "Verbose logging for Intel Management Engine"
1080 Enable verbose logging for Intel Management Engine driver that
1081 is present on Intel 6-series chipsets.
1085 bool "Built-in low-level shell"
1088 If enabled, you will have a low level shell to examine your machine.
1089 Put llshell() in your (romstage) code to start the shell.
1090 See src/arch/x86/llshell/llshell.inc for details.
1093 bool "Trace function calls"
1096 If enabled, every function will print information to console once
1097 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1098 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1099 of calling function. Please note some printk releated functions
1100 are omitted from trace to have good looking console dumps.
1103 config LIFT_BSP_APIC_ID
1107 # These probably belong somewhere else, but they are needed somewhere.
1108 config AP_CODE_IN_CAR
1112 config RAMINIT_SYSINFO
1116 config ENABLE_APIC_EXT_ID
1120 config WARNINGS_ARE_ERRORS
1124 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1125 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1126 # mutually exclusive. One of these options must be selected in the
1127 # mainboard Kconfig if the chipset supports enabling and disabling of
1128 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1129 # in mainboard/Kconfig to know if the button should be enabled or not.
1131 config POWER_BUTTON_DEFAULT_ENABLE
1134 Select when the board has a power button which can optionally be
1135 disabled by the user.
1137 config POWER_BUTTON_DEFAULT_DISABLE
1140 Select when the board has a power button which can optionally be
1141 enabled by the user, e.g. when the board ships with a jumper over
1142 the power switch contacts.
1144 config POWER_BUTTON_FORCE_ENABLE
1147 Select when the board requires that the power button is always
1150 config POWER_BUTTON_FORCE_DISABLE
1153 Select when the board requires that the power button is always
1154 disabled, e.g. when it has been hardwired to ground.
1156 config POWER_BUTTON_IS_OPTIONAL
1158 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1159 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1161 Internal option that controls ENABLE_POWER_BUTTON visibility.
1163 source src/Kconfig.deprecated_options
1164 source src/vendorcode/Kconfig