2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
65 Use the GNU Compiler Collection (GCC) to build coreboot.
67 For details see http://gcc.gnu.org.
69 config COMPILER_LLVM_CLANG
72 Use LLVM/clang to build coreboot.
74 For details see http://clang.llvm.org.
79 bool "Allow building with any toolchain"
81 depends on COMPILER_GCC
83 Many toolchains break when building coreboot since it uses quite
84 unusual linker features. Unless developers explicitely request it,
85 we'll have to assume that they use their distro compiler by mistake.
86 Make sure that using patched compilers is a conscious decision.
89 bool "Use ccache to speed up (re)compilation"
92 Enables the use of ccache for faster builds.
94 Requires the ccache utility in your system $PATH.
96 For details see https://ccache.samba.org.
99 bool "Generate flashmap descriptor parser using flex and bison"
102 Enable this option if you are working on the flashmap descriptor
103 parser and made changes to fmd_scanner.l or fmd_parser.y.
105 Otherwise, say N to use the provided pregenerated scanner/parser.
107 config SCONFIG_GENPARSER
108 bool "Generate SCONFIG parser using flex and bison"
111 Enable this option if you are working on the sconfig device tree
112 parser and made changes to sconfig.l or sconfig.y.
114 Otherwise, say N to use the provided pregenerated scanner/parser.
116 config USE_OPTION_TABLE
117 bool "Use CMOS for configuration values"
119 depends on HAVE_OPTION_TABLE
121 Enable this option if coreboot shall read options from the "CMOS"
122 NVRAM instead of using hard-coded values.
124 config STATIC_OPTION_TABLE
125 bool "Load default configuration values into CMOS on each boot"
127 depends on USE_OPTION_TABLE
129 Enable this option to reset "CMOS" NVRAM values to default on
130 every boot. Use this if you want the NVRAM configuration to
131 never be modified from its default values.
133 config UNCOMPRESSED_RAMSTAGE
137 config COMPRESS_RAMSTAGE
138 bool "Compress ramstage with LZMA"
139 default y if !UNCOMPRESSED_RAMSTAGE
142 Compress ramstage to save memory in the flash image. Note
143 that decompression might slow down booting if the boot flash
144 is connected through a slow link (i.e. SPI).
146 config INCLUDE_CONFIG_FILE
147 bool "Include the coreboot .config file into the ROM image"
150 Include the .config file that was used to compile coreboot
151 in the (CBFS) ROM image. This is useful if you want to know which
152 options were used to build a specific coreboot.rom image.
154 Saying Y here will increase the image size by 2-3KB.
156 You can use the following command to easily list the options:
158 grep -a CONFIG_ coreboot.rom
160 Alternatively, you can also use cbfstool to print the image
161 contents (including the raw 'config' item we're looking for).
165 $ cbfstool coreboot.rom print
166 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
170 Name Offset Type Size
171 cmos_layout.bin 0x0 cmos layout 1159
172 fallback/romstage 0x4c0 stage 339756
173 fallback/ramstage 0x53440 stage 186664
174 fallback/payload 0x80dc0 payload 51526
175 config 0x8d740 raw 3324
176 (empty) 0x8e480 null 3610440
178 config EARLY_CBMEM_INIT
179 def_bool !LATE_CBMEM_INIT
181 config COLLECT_TIMESTAMPS
182 bool "Create a table of timestamps collected during boot"
185 Make coreboot create a table of timer-ID/timer-value pairs to
186 allow measuring time spent at different phases of the boot process.
188 config HAS_PRECBMEM_TIMESTAMP_REGION
189 bool "Timestamp region exists for pre-cbmem timestamps"
190 default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM
192 A separate region is maintained to allow storing of timestamps before
193 cbmem comes up. This is useful for storing timestamps across different
197 bool "Allow use of binary-only repository"
200 This draws in the blobs repository, which contains binary files that
201 might be required for some chipsets or boards.
202 This flag ensures that a "Free" option remains available for users.
205 bool "Code coverage support"
206 depends on COMPILER_GCC
209 Add code coverage support for coreboot. This will store code
210 coverage information in CBMEM for extraction from user space.
213 config RELOCATABLE_MODULES
217 If RELOCATABLE_MODULES is selected then support is enabled for
218 building relocatable modules in the RAM stage. Those modules can be
219 loaded anywhere and all the relocations are handled automatically.
221 config RELOCATABLE_RAMSTAGE
222 depends on EARLY_CBMEM_INIT
223 bool "Build the ramstage to be relocatable in 32-bit address space."
225 select RELOCATABLE_MODULES
227 The reloctable ramstage support allows for the ramstage to be built
228 as a relocatable module. The stage loader can identify a place
229 out of the OS way so that copying memory is unnecessary during an S3
230 wake. When selecting this option the romstage is responsible for
231 determing a stack location to use for loading the ramstage.
233 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
234 depends on RELOCATABLE_RAMSTAGE
235 bool "Cache the relocated ramstage outside of cbmem."
238 The relocated ramstage is saved in an area specified by the
239 by the board and/or chipset.
241 config FLASHMAP_OFFSET
242 hex "Flash Map Offset"
243 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
244 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
245 default CBFS_SIZE if !ARCH_X86
248 Offset of flash map in firmware image
250 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
252 prompt "Bootblock behaviour"
253 default BOOTBLOCK_SIMPLE
255 config BOOTBLOCK_SIMPLE
256 bool "Always load fallback"
258 config BOOTBLOCK_NORMAL
259 bool "Switch to normal if CMOS says so"
263 # To be selected by arch, SoC or mainboard if it does not want use the normal
264 # src/lib/bootblock.c#main() C entry point.
265 config BOOTBLOCK_CUSTOM
269 config BOOTBLOCK_SOURCE
271 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
272 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
274 config SKIP_MAX_REBOOT_CNT_CLEAR
275 bool "Do not clear reboot count after successful boot"
277 depends on BOOTBLOCK_NORMAL
279 Do not clear the reboot count immediately after successful boot.
280 Set to allow the payload to control normal/fallback image recovery.
281 Note that it is the responsibility of the payload to reset the
282 normal boot bit to 1 after each successsful boot.
285 bool "Update existing coreboot.rom image"
288 If this option is enabled, no new coreboot.rom file
289 is created. Instead it is expected that there already
290 is a suitable file for further processing.
291 The bootblock will not be modified.
293 config GENERIC_GPIO_LIB
297 If enabled, compile the generic GPIO library. A "generic" GPIO
298 implies configurability usually found on SoCs, particularly the
299 ability to control internal pull resistors.
305 Mainboards that can read a board ID from the hardware straps
306 (ie. GPIO) select this configuration option.
308 config BOARD_ID_MANUAL
311 depends on !BOARD_ID_AUTO
313 If you want to maintain a board ID, but the hardware does not
314 have straps to automatically determine the ID, you can say Y
315 here and add a file named 'board_id' to CBFS. If you don't know
316 what this is about, say N.
318 config BOARD_ID_STRING
321 depends on BOARD_ID_MANUAL
323 This string is placed in the 'board_id' CBFS file for indicating
326 config RAM_CODE_SUPPORT
330 If enabled, coreboot discovers RAM configuration (value obtained by
331 reading board straps) and stores it in coreboot table.
333 config BOOTSPLASH_IMAGE
334 bool "Add a bootsplash image"
336 Select this option if you have a bootsplash image that you would
337 like to add to your ROM.
339 This will only add the image to the ROM. To actually run it check
340 options under 'Display' section.
342 config BOOTSPLASH_FILE
343 string "Bootsplash path and filename"
344 depends on BOOTSPLASH_IMAGE
345 default "bootsplash.jpg"
347 The path and filename of the file to use as graphical bootsplash
348 screen. The file format has to be jpg.
352 source "src/acpi/Kconfig"
356 source "src/mainboard/Kconfig"
359 hex "Size of CBFS filesystem in ROM"
360 default 0x100000 if HAVE_INTEL_FIRMWARE || \
361 NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
362 NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
363 NORTHBRIDGE_INTEL_SANDYBRIDGE || \
364 NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
366 default 0x200000 if SOC_INTEL_SKYLAKE
369 This is the part of the ROM actually managed by CBFS, located at the
370 end of the ROM (passed through cbfstool -o) on x86 and at at the start
371 of the ROM (passed through cbfstool -s) everywhere else. It defaults
372 to span the whole ROM on all but Intel systems that use an Intel Firmware
373 Descriptor. It can be overridden to make coreboot live alongside other
374 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
379 config SYSTEM_TYPE_LAPTOP
386 source "src/soc/*/*/Kconfig"
388 source "src/cpu/Kconfig"
389 comment "Northbridge"
390 source "src/northbridge/*/*/Kconfig"
391 comment "Southbridge"
392 source "src/southbridge/*/*/Kconfig"
394 source "src/superio/*/Kconfig"
395 comment "Embedded Controllers"
396 source "src/ec/acpi/Kconfig"
397 source "src/ec/*/*/Kconfig"
398 source "src/drivers/intel/fsp1_0/Kconfig"
400 source "src/southbridge/intel/common/firmware/Kconfig"
401 source "src/vendorcode/*/Kconfig"
403 source "src/arch/*/Kconfig"
407 source "src/device/Kconfig"
409 menu "Generic Drivers"
410 source "src/drivers/*/Kconfig"
420 select LPC_TPM if ARCH_X86
421 select I2C_TPM if ARCH_ARM
422 select I2C_TPM if ARCH_ARM64
424 Enable this option to enable TPM support in coreboot.
439 default 0x1000 if ARCH_X86
446 config MMCONF_SUPPORT_DEFAULT
450 config MMCONF_SUPPORT
454 config BOOTMODE_STRAPS
458 source "src/console/Kconfig"
460 config HAVE_ACPI_RESUME
464 config HAVE_HARD_RESET
468 This variable specifies whether a given board has a hard_reset
469 function, no matter if it's provided by board code or chipset code.
471 config HAVE_MONOTONIC_TIMER
474 The board/chipset provides a monotonic timer.
476 config GENERIC_UDELAY
478 depends on HAVE_MONOTONIC_TIMER
480 The board/chipset uses a generic udelay function utilizing the
485 depends on HAVE_MONOTONIC_TIMER
487 Provide a timer queue for performing time-based callbacks.
489 config COOP_MULTITASKING
491 depends on TIMER_QUEUE && ARCH_X86
493 Cooperative multitasking allows callbacks to be multiplexed on the
494 main thread of ramstage. With this enabled it allows for multiple
495 execution paths to take place when they have udelay() calls within
501 depends on COOP_MULTITASKING
503 How many execution threads to cooperatively multitask with.
505 config HAVE_OPTION_TABLE
509 This variable specifies whether a given board has a cmos.layout
510 file containing NVRAM/CMOS bit definitions.
511 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
517 config HAVE_SMI_HANDLER
521 config PCI_IO_CFG_EXT
529 config CACHE_ROM_SIZE_OVERRIDE
533 # TODO: Can probably be removed once all chipsets have kconfig options for it.
538 config USE_WATCHDOG_ON_BOOT
546 Build board-specific VGA code.
552 Enable Unified Memory Architecture for graphics.
554 config HAVE_ACPI_TABLES
557 This variable specifies whether a given board has ACPI table support.
558 It is usually set in mainboard/*/Kconfig.
563 This variable specifies whether a given board has MP table support.
564 It is usually set in mainboard/*/Kconfig.
565 Whether or not the MP table is actually generated by coreboot
566 is configurable by the user via GENERATE_MP_TABLE.
568 config HAVE_PIRQ_TABLE
571 This variable specifies whether a given board has PIRQ table support.
572 It is usually set in mainboard/*/Kconfig.
573 Whether or not the PIRQ table is actually generated by coreboot
574 is configurable by the user via GENERATE_PIRQ_TABLE.
576 config MAX_PIRQ_LINKS
580 This variable specifies the number of PIRQ interrupt links which are
581 routable. On most chipsets, this is 4, INTA through INTD. Some
582 chipsets offer more than four links, commonly up to INTH. They may
583 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
584 table specifies links greater than 4, pirq_route_irqs will not
585 function properly, unless this variable is correctly set.
591 #These Options are here to avoid "undefined" warnings.
592 #The actual selection and help texts are in the following menu.
596 config GENERATE_MP_TABLE
597 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
599 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
601 Generate an MP table (conforming to the Intel MultiProcessor
602 specification 1.4) for this board.
606 config GENERATE_PIRQ_TABLE
607 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
609 default HAVE_PIRQ_TABLE
611 Generate a PIRQ table for this board.
615 config GENERATE_SMBIOS_TABLES
617 bool "Generate SMBIOS tables"
620 Generate SMBIOS tables for this board.
624 config SMBIOS_PROVIDED_BY_MOBO
628 config MAINBOARD_SERIAL_NUMBER
629 string "SMBIOS Serial Number"
630 depends on GENERATE_SMBIOS_TABLES
631 depends on !SMBIOS_PROVIDED_BY_MOBO
634 The Serial Number to store in SMBIOS structures.
636 config MAINBOARD_VERSION
637 string "SMBIOS Version Number"
638 depends on GENERATE_SMBIOS_TABLES
639 depends on !SMBIOS_PROVIDED_BY_MOBO
642 The Version Number to store in SMBIOS structures.
644 config MAINBOARD_SMBIOS_MANUFACTURER
645 string "SMBIOS Manufacturer"
646 depends on GENERATE_SMBIOS_TABLES
647 depends on !SMBIOS_PROVIDED_BY_MOBO
648 default MAINBOARD_VENDOR
650 Override the default Manufacturer stored in SMBIOS structures.
652 config MAINBOARD_SMBIOS_PRODUCT_NAME
653 string "SMBIOS Product name"
654 depends on GENERATE_SMBIOS_TABLES
655 depends on !SMBIOS_PROVIDED_BY_MOBO
656 default MAINBOARD_PART_NUMBER
658 Override the default Product name stored in SMBIOS structures.
665 prompt "Add a payload"
666 default PAYLOAD_NONE if !ARCH_X86
667 default PAYLOAD_SEABIOS if ARCH_X86
672 Select this option if you want to create an "empty" coreboot
673 ROM image for a certain mainboard, i.e. a coreboot ROM image
674 which does not yet contain a payload.
676 For such an image to be useful, you have to use 'cbfstool'
677 to add a payload to the ROM image later.
680 bool "An ELF executable payload"
682 Select this option if you have a payload image (an ELF file)
683 which coreboot should run as soon as the basic hardware
684 initialization is completed.
686 You will be able to specify the location and file name of the
689 source "payloads/external/*/Kconfig.name"
693 source "payloads/external/*/Kconfig"
696 string "Payload path and filename"
697 depends on PAYLOAD_ELF
698 default "payload.elf"
700 The path and filename of the ELF executable file to use as payload.
702 # TODO: Defined if no payload? Breaks build?
703 config COMPRESSED_PAYLOAD_LZMA
704 bool "Use LZMA compression for payloads"
706 depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
708 In order to reduce the size payloads take up in the ROM chip
709 coreboot can compress them using the LZMA algorithm.
715 # TODO: Better help text and detailed instructions.
717 bool "GDB debugging support"
720 If enabled, you will be able to set breakpoints for gdb debugging.
721 See src/arch/x86/lib/c_start.S for details.
724 bool "Wait for a GDB connection"
728 If enabled, coreboot will wait for a GDB connection.
731 bool "Halt when hitting a BUG() or assertion error"
734 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
737 bool "Output verbose CBFS debug messages"
740 This option enables additional CBFS related debug messages.
742 config HAVE_DEBUG_RAM_SETUP
745 config DEBUG_RAM_SETUP
746 bool "Output verbose RAM init debug messages"
748 depends on HAVE_DEBUG_RAM_SETUP
750 This option enables additional RAM init related debug messages.
751 It is recommended to enable this when debugging issues on your
752 board which might be RAM init related.
754 Note: This option will increase the size of the coreboot image.
758 config HAVE_DEBUG_CAR
763 depends on HAVE_DEBUG_CAR
765 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
766 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
767 # printk(BIOS_DEBUG, ...) calls.
769 bool "Output verbose Cache-as-RAM debug messages"
771 depends on HAVE_DEBUG_CAR
773 This option enables additional CAR related debug messages.
777 bool "Check PIRQ table consistency"
779 depends on GENERATE_PIRQ_TABLE
783 config HAVE_DEBUG_SMBUS
787 bool "Output verbose SMBus debug messages"
789 depends on HAVE_DEBUG_SMBUS
791 This option enables additional SMBus (and SPD) debug messages.
793 Note: This option will increase the size of the coreboot image.
798 bool "Output verbose SMI debug messages"
800 depends on HAVE_SMI_HANDLER
801 select SPI_FLASH_SMM if SPI_CONSOLE
803 This option enables additional SMI related debug messages.
805 Note: This option will increase the size of the coreboot image.
809 config DEBUG_SMM_RELOCATION
810 bool "Debug SMM relocation code"
812 depends on HAVE_SMI_HANDLER
814 This option enables additional SMM handler relocation related
817 Note: This option will increase the size of the coreboot image.
821 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
822 # printk(BIOS_DEBUG, ...) calls.
824 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
828 This option enables additional malloc related debug messages.
830 Note: This option will increase the size of the coreboot image.
834 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
835 # printk(BIOS_DEBUG, ...) calls.
837 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
841 This option enables additional ACPI related debug messages.
843 Note: This option will slightly increase the size of the coreboot image.
847 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
848 # printk(BIOS_DEBUG, ...) calls.
849 config REALMODE_DEBUG
850 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
853 depends on PCI_OPTION_ROM_RUN_REALMODE
855 This option enables additional x86emu related debug messages.
857 Note: This option will increase the time to emulate a ROM.
862 bool "Output verbose x86emu debug messages"
864 depends on PCI_OPTION_ROM_RUN_YABEL
866 This option enables additional x86emu related debug messages.
868 Note: This option will increase the size of the coreboot image.
872 config X86EMU_DEBUG_JMP
873 bool "Trace JMP/RETF"
875 depends on X86EMU_DEBUG
877 Print information about JMP and RETF opcodes from x86emu.
879 Note: This option will increase the size of the coreboot image.
883 config X86EMU_DEBUG_TRACE
884 bool "Trace all opcodes"
886 depends on X86EMU_DEBUG
888 Print _all_ opcodes that are executed by x86emu.
890 WARNING: This will produce a LOT of output and take a long time.
892 Note: This option will increase the size of the coreboot image.
896 config X86EMU_DEBUG_PNP
897 bool "Log Plug&Play accesses"
899 depends on X86EMU_DEBUG
901 Print Plug And Play accesses made by option ROMs.
903 Note: This option will increase the size of the coreboot image.
907 config X86EMU_DEBUG_DISK
910 depends on X86EMU_DEBUG
912 Print Disk I/O related messages.
914 Note: This option will increase the size of the coreboot image.
918 config X86EMU_DEBUG_PMM
921 depends on X86EMU_DEBUG
923 Print messages related to POST Memory Manager (PMM).
925 Note: This option will increase the size of the coreboot image.
930 config X86EMU_DEBUG_VBE
931 bool "Debug VESA BIOS Extensions"
933 depends on X86EMU_DEBUG
935 Print messages related to VESA BIOS Extension (VBE) functions.
937 Note: This option will increase the size of the coreboot image.
941 config X86EMU_DEBUG_INT10
942 bool "Redirect INT10 output to console"
944 depends on X86EMU_DEBUG
946 Let INT10 (i.e. character output) calls print messages to debug output.
948 Note: This option will increase the size of the coreboot image.
952 config X86EMU_DEBUG_INTERRUPTS
953 bool "Log intXX calls"
955 depends on X86EMU_DEBUG
957 Print messages related to interrupt handling.
959 Note: This option will increase the size of the coreboot image.
963 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
964 bool "Log special memory accesses"
966 depends on X86EMU_DEBUG
968 Print messages related to accesses to certain areas of the virtual
969 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
971 Note: This option will increase the size of the coreboot image.
975 config X86EMU_DEBUG_MEM
976 bool "Log all memory accesses"
978 depends on X86EMU_DEBUG
980 Print memory accesses made by option ROM.
981 Note: This also includes accesses to fetch instructions.
983 Note: This option will increase the size of the coreboot image.
987 config X86EMU_DEBUG_IO
988 bool "Log IO accesses"
990 depends on X86EMU_DEBUG
992 Print I/O accesses made by option ROM.
994 Note: This option will increase the size of the coreboot image.
998 config X86EMU_DEBUG_TIMINGS
999 bool "Output timing information"
1001 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1003 Print timing information needed by i915tool.
1008 bool "Output verbose TPM debug messages"
1012 This option enables additional TPM related debug messages.
1014 config DEBUG_SPI_FLASH
1015 bool "Output verbose SPI flash debug messages"
1017 depends on SPI_FLASH
1019 This option enables additional SPI flash related debug messages.
1021 config DEBUG_USBDEBUG
1022 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1026 This option enables additional USB 2.0 debug dongle related messages.
1028 Select this to debug the connection of usbdebug dongle. Note that
1029 you need some other working console to receive the messages.
1031 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1032 # Only visible with the right southbridge and loglevel.
1033 config DEBUG_INTEL_ME
1034 bool "Verbose logging for Intel Management Engine"
1037 Enable verbose logging for Intel Management Engine driver that
1038 is present on Intel 6-series chipsets.
1042 bool "Trace function calls"
1045 If enabled, every function will print information to console once
1046 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1047 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1048 of calling function. Please note some printk related functions
1049 are omitted from trace to have good looking console dumps.
1051 config DEBUG_COVERAGE
1052 bool "Debug code coverage"
1056 If enabled, the code coverage hooks in coreboot will output some
1057 information about the coverage data that is dumped.
1061 # These probably belong somewhere else, but they are needed somewhere.
1062 config ENABLE_APIC_EXT_ID
1066 config WARNINGS_ARE_ERRORS
1070 # TODO: Remove this when all platforms are fixed.
1071 config IASL_WARNINGS_ARE_ERRORS
1074 Select to Fail the build if a IASL generates a warning.
1075 This will be defaulted to disabled for the platforms that
1076 currently fail. This allows the REST of the platforms to
1077 have this check enabled while we're working to get those
1080 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1083 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1084 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1085 # mutually exclusive. One of these options must be selected in the
1086 # mainboard Kconfig if the chipset supports enabling and disabling of
1087 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1088 # in mainboard/Kconfig to know if the button should be enabled or not.
1090 config POWER_BUTTON_DEFAULT_ENABLE
1093 Select when the board has a power button which can optionally be
1094 disabled by the user.
1096 config POWER_BUTTON_DEFAULT_DISABLE
1099 Select when the board has a power button which can optionally be
1100 enabled by the user, e.g. when the board ships with a jumper over
1101 the power switch contacts.
1103 config POWER_BUTTON_FORCE_ENABLE
1106 Select when the board requires that the power button is always
1109 config POWER_BUTTON_FORCE_DISABLE
1112 Select when the board requires that the power button is always
1113 disabled, e.g. when it has been hardwired to ground.
1115 config POWER_BUTTON_IS_OPTIONAL
1117 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1118 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1120 Internal option that controls ENABLE_POWER_BUTTON visibility.
1126 Internal option that controls whether we compile in register scripts.
1128 config MAX_REBOOT_CNT
1132 Internal option that sets the maximum number of bootblock executions allowed
1133 with the normal image enabled before assuming the normal image is defective
1134 and switching to the fallback image.