src/mainboard/siemens/sitemp_g1p1/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Siemens AG, Inc.
   6  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <arch/io.h>
  22 #include <arch/interrupt.h>
  23 #include <delay.h>
  24 #include <cpu/x86/msr.h>
  25 #include <cpu/amd/mtrr.h>
  26 #include <device/pci_def.h>
  27 #include <pc80/mc146818rtc.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <southbridge/amd/sb600/sb600.h>
  30 #include <southbridge/amd/rs690/chip.h>
  31 #include <southbridge/amd/rs690/rs690.h>
  32 #include <superio/ite/it8712f/it8712f.h>
  33 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
  34 #include <x86emu/x86emu.h>
  35 #endif
  36 #include "int15_func.h"
  37 #include "mainboard.h"
  38
  39 // ****LCD panel ID support: *****
  40 // Callback Sub-Function 00h - Get LCD Panel ID
  41 #define PANEL_TABLE_ID_NO       0 // no LCD
  42 #define PANEL_TABLE_ID1         1 // 1024x768_65MHz_Dual
  43 #define PANEL_TABLE_ID2         2 // 920x1200_162MHz
  44 #define PANEL_TABLE_ID3         3 // 600x1200_162MHz
  45 #define PANEL_TABLE_ID4         4 // 1024x768_65MHz
  46 #define PANEL_TABLE_ID5         5 // 1400x1050_108MHz
  47 #define PANEL_TABLE_ID6         6 // 1680x1050_119MHz
  48 #define PANEL_TABLE_ID7         7 // 2048x1536_164MHz
  49 #define PANEL_TABLE_ID8         8 // 1280x1024_108MHz
  50 #define PANEL_TABLE_ID9         9 // 1366x768_86MHz_chimei_V32B1L01
  51
  52 // Callback Sub-Function 05h - Select Boot-up TV Standard
  53 #define TV_MODE_00      0x00    /* NTSC */
  54 #define TV_MODE_01      0x01    /* PAL */
  55 #define TV_MODE_02      0x02    /* PALM */
  56 #define TV_MODE_03      0x03    /* PAL60 */
  57 #define TV_MODE_04      0x04    /* NTSCJ */
  58 #define TV_MODE_05      0x05    /* PALCN */
  59 #define TV_MODE_06      0x06    /* PALN */
  60 #define TV_MODE_09      0x09    /* SCART-RGB */
  61 #define TV_MODE_NO      0xff    /* No TV Support */
  62
  63 #define PLX_VIDDID 0x861610b5
  64
  65 /* 7475 Common Registers */
  66 #define REG_DEVREV2             0x12    /* ADT7490 only */
  67 #define REG_VTT                 0x1E    /* ADT7490 only */
  68 #define REG_EXTEND3             0x1F    /* ADT7490 only */
  69 #define REG_VOLTAGE_BASE        0x20
  70 #define REG_TEMP_BASE           0x25
  71 #define REG_TACH_BASE           0x28
  72 #define REG_PWM_BASE            0x30
  73 #define REG_PWM_MAX_BASE        0x38
  74 #define REG_DEVID               0x3D
  75 #define REG_VENDID              0x3E
  76 #define REG_DEVID2              0x3F
  77 #define REG_STATUS1             0x41
  78 #define REG_STATUS2             0x42
  79 #define REG_VID                 0x43    /* ADT7476 only */
  80 #define REG_VOLTAGE_MIN_BASE    0x44
  81 #define REG_VOLTAGE_MAX_BASE    0x45
  82 #define REG_TEMP_MIN_BASE       0x4E
  83 #define REG_TEMP_MAX_BASE       0x4F
  84 #define REG_TACH_MIN_BASE       0x54
  85 #define REG_PWM_CONFIG_BASE     0x5C
  86 #define REG_TEMP_TRANGE_BASE    0x5F
  87 #define REG_PWM_MIN_BASE        0x64
  88 #define REG_TEMP_TMIN_BASE      0x67
  89 #define REG_TEMP_THERM_BASE     0x6A
  90 #define REG_REMOTE1_HYSTERSIS   0x6D
  91 #define REG_REMOTE2_HYSTERSIS   0x6E
  92 #define REG_TEMP_OFFSET_BASE    0x70
  93 #define REG_CONFIG2             0x73
  94 #define REG_EXTEND1             0x76
  95 #define REG_EXTEND2             0x77
  96 #define REG_CONFIG1                             0x40    // ADT7475
  97 #define REG_CONFIG3             0x78
  98 #define REG_CONFIG5             0x7C
  99 #define REG_CONFIG6                             0x10    // ADT7475
 100 #define REG_CONFIG7                             0x11    // ADT7475
 101 #define REG_CONFIG4             0x7D
 102 #define REG_STATUS4             0x81    /* ADT7490 only */
 103 #define REG_VTT_MIN             0x84    /* ADT7490 only */
 104 #define REG_VTT_MAX             0x86    /* ADT7490 only */
 105
 106 #define VID_VIDSEL              0x80    /* ADT7476 only */
 107
 108 #define CONFIG2_ATTN            0x20
 109 #define CONFIG3_SMBALERT        0x01
 110 #define CONFIG3_THERM           0x02
 111 #define CONFIG4_PINFUNC         0x03
 112 #define CONFIG4_MAXDUTY         0x08
 113 #define CONFIG4_ATTN_IN10       0x30
 114 #define CONFIG4_ATTN_IN43       0xC0
 115 #define CONFIG5_TWOSCOMP        0x01
 116 #define CONFIG5_TEMPOFFSET      0x02
 117 #define CONFIG5_VIDGPIO         0x10    /* ADT7476 only */
 118 #define REMOTE1                                 0
 119 #define LOCAL                                   1
 120 #define REMOTE2                                 2
 121
 122 /* ADT7475 Settings */
 123 #define ADT7475_VOLTAGE_COUNT   5       /* Not counting Vtt */
 124 #define ADT7475_TEMP_COUNT      3
 125 #define ADT7475_TACH_COUNT      4
 126 #define ADT7475_PWM_COUNT       3
 127
 128 /* Macros to easily index the registers */
 129 #define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2))
 130 #define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2))
 131
 132 #define PWM_REG(idx) (REG_PWM_BASE + (idx))
 133 #define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx))
 134 #define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx))
 135 #define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx))
 136
 137 #define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx))
 138 #define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2))
 139 #define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2))
 140
 141 #define TEMP_REG(idx) (REG_TEMP_BASE + (idx))
 142 #define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2))
 143 #define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2))
 144 #define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx))
 145 #define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx))
 146 #define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx))
 147 #define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx))
 148
 149 #define SMBUS_IO_BASE 0x1000
 150 #define ADT7475_ADDRESS 0x2E
 151
 152 #define D_OPEN  (1 << 6)
 153 #define D_CLS           (1 << 5)
 154 #define D_LCK           (1 << 4)
 155 #define G_SMRAME        (1 << 3)
 156 #define A_BASE_SEG      ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
 157
 158 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 159 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 160
 161 static u32 smbus_io_base = SMBUS_IO_BASE;
 162 static u32 adt7475_address = ADT7475_ADDRESS;
 163
 164 /* Macro to read the registers */
 165 #define adt7475_read_byte(reg) \
 166         do_smbus_read_byte(smbus_io_base, adt7475_address, reg)
 167
 168 #define adt7475_write_byte(reg, val) \
 169         do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val)
 170
 171 #define TWOS_COMPL 1
 172
 173 struct __table__{
 174         const char *info;
 175         u8 val;
 176 };
 177
 178 struct __table__ dutycycles[] = {
 179         {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73},
 180         {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4},
 181         {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5},
 182         {"100%", 0xff}
 183 };
 184 #define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__)
 185 #define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix
 186 #define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range"
 187 #if TWOS_COMPL == 0
 188 struct __table__ temperatures[] = {
 189         {"30C", 0x5e},{"35C", 0x63},{"40C", 0x68},{"45C", 0x6d},{"50C", 0x72},
 190         {"55C", 0x77},{"60C", 0x7c},{"65C", 0x81},{"70C", 0x86},{"75C", 0x8b},
 191         {"80C", 0x90}
 192 };
 193 #else
 194 struct __table__ temperatures[] = {
 195         {"30C", 30},{"35C", 35},{"40C", 40},{"45C", 45},{"50C", 50},
 196         {"55C", 55},{"60C", 60},{"65C", 65},{"70C", 70},{"75C", 75},
 197         {"80C", 80}
 198 };
 199 #endif
 200 // FIXME: implicit conversion from 'double' to 'int'
 201 // int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0};
 202 int trange[] = {2,2,3,4,5,6,8,10,13,16,20,26,32,40,53,80};
 203
 204 #define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__)
 205 #define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix
 206 #define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range"
 207
 208 struct fan_control {
 209                 unsigned int enable : 1;
 210                 u8 polarity;
 211                 u8 t_min;
 212                 u8 t_max;
 213                 u8 pwm_min;
 214                 u8 pwm_max;
 215                 u8 t_range;
 216 };
 217 /* ############################################################################################# */
 218 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
 219 static int int15_handler(void)
 220 {
 221 #define BOOT_DISPLAY_DEFAULT    0
 222 #define BOOT_DISPLAY_CRT        (1 << 0)
 223 #define BOOT_DISPLAY_TV         (1 << 1)
 224 #define BOOT_DISPLAY_EFP        (1 << 2)
 225 #define BOOT_DISPLAY_LCD        (1 << 3)
 226 #define BOOT_DISPLAY_CRT2       (1 << 4)
 227 #define BOOT_DISPLAY_TV2        (1 << 5)
 228 #define BOOT_DISPLAY_EFP2       (1 << 6)
 229 #define BOOT_DISPLAY_LCD2       (1 << 7)
 230
 231         printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
 232                           __func__, X86_AX, X86_BX, X86_CX, X86_DX);
 233
 234         switch (X86_AX) {
 235         case 0x4e08: /* Boot Display */
 236             switch (X86_BX) {
 237                 case 0x80:
 238                         X86_AX &= ~(0xff); // Success
 239                         X86_BX &= ~(0xff);
 240                         printk(BIOS_DEBUG, "Integrated System Information\n");
 241                         break;
 242                 case 0x00:
 243                         X86_AX &= ~(0xff);
 244                         X86_BX = 0x00;
 245                         printk(BIOS_DEBUG, "Panel ID = 0\n");
 246                         break;
 247                 case 0x05:
 248                         X86_AX &= ~(0xff);
 249                         X86_BX = 0xff;
 250                         printk(BIOS_DEBUG, "TV = off\n");
 251                         break;
 252                 default:
 253                         return 0;
 254                 }
 255                 break;
 256         case 0x5f35: /* Boot Display */
 257                 X86_AX = 0x005f; // Success
 258                 X86_CL = BOOT_DISPLAY_DEFAULT;
 259                 break;
 260         case 0x5f40: /* Boot Panel Type */
 261                 // M.x86.R_AX = 0x015f; // Supported but failed
 262                 X86_AX = 0x005f; // Success
 263                 X86_CL = 3; // Display ID
 264                 break;
 265         default:
 266                 /* Interrupt was not handled */
 267                 return 0;
 268         }
 269
 270         /* Interrupt handled */
 271         return 1;
 272 }
 273 #endif
 274 /* ############################################################################################# */
 275
 276 static u8 calc_trange(u8 t_min, u8 t_max) {
 277
 278         u8 prev;
 279         int i;
 280         int diff = t_max - t_min;
 281
 282         // walk through the trange table
 283         for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) {
 284                 if( trange[i] < diff ) {
 285                         prev = i; // save last val
 286                         continue;
 287                 }
 288                 if( diff == trange[i] ) return i;
 289                 if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index
 290                 return i;
 291         }
 292         return prev;
 293 }
 294
 295 /********************************************************
 296 * sina uses SB600 GPIO9 to detect IDE_DMA66.
 297 * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 298 * get the cable type, 40 pin or 80 pin?
 299 ********************************************************/
 300 static void cable_detect(void)
 301 {
 302
 303         u8 byte;
 304         struct device *sm_dev;
 305         struct device *ide_dev;
 306
 307         /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */
 308         printk(BIOS_DEBUG, "%s.\n", __func__);
 309         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 310
 311         byte = pci_read_config8(sm_dev, 0xA9);
 312         byte |= (1 << 5);       /* Set Gpio9 as input */
 313         pci_write_config8(sm_dev, 0xA9, byte);
 314
 315         /* IDE Controller (Device 20, Function 1) on SB600 */
 316         ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
 317
 318         byte = pci_read_config8(ide_dev, 9);
 319         printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility");
 320
 321         byte = pci_read_config8(ide_dev, 0x56);
 322         byte &= ~(7 << 0);
 323         if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) )
 324                 byte |= 2 << 0; /* mode 2 */
 325         else
 326                 byte |= 5 << 0; /* mode 5 */
 327         printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0));
 328         pci_write_config8(ide_dev, 0x56, byte);
 329 }
 330
 331 /**
 332  * @brief Detect the ADT7475 device
 333  *
 334  */
 335
 336 static const char * adt7475_detect( void ) {
 337
 338         int vendid, devid, devid2;
 339         const char *name = NULL;
 340
 341         vendid = adt7475_read_byte(REG_VENDID);
 342         devid2 = adt7475_read_byte(REG_DEVID2);
 343         if (vendid != 0x41 || (devid2 & 0xf8) != 0x68) /* Analog Devices */
 344                 return name;
 345
 346         devid = adt7475_read_byte(REG_DEVID);
 347         if (devid == 0x73)
 348                 name = "adt7473";
 349         else if (devid == 0x75 && adt7475_address == 0x2e)
 350                 name = "adt7475";
 351         else if (devid == 0x76)
 352                 name = "adt7476";
 353         else if ((devid2 & 0xfc) == 0x6c)
 354                 name = "adt7490";
 355
 356         return name;
 357 }
 358
 359 // thermal control defaults
 360 const struct fan_control cpu_fan_control_defaults = {
 361         .enable = 0, // disable by default
 362         .polarity = 0, // high by default
 363         .t_min = 3, // default = 45°C
 364         .t_max = 7, // 65°C
 365         .pwm_min = 1, // default dutycycle = 30%
 366         .pwm_max = 13, // 90%
 367 };
 368 const struct fan_control case_fan_control_defaults = {
 369         .enable = 0, // disable by default
 370         .polarity = 0, // high by default
 371         .t_min = 2, // default = 40°C
 372         .t_max = 8, // 70°C
 373         .pwm_min = 0, // default dutycycle = 25%
 374         .pwm_max = 13, // 90%
 375 };
 376
 377 static void pm_init( void )
 378 {
 379         u16 word;
 380         u8 byte;
 381         device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 382
 383         /* set SB600 GPIO 64 to GPIO with pull-up */
 384         byte = pm2_ioread(0x42);
 385         byte &= 0x3f;
 386         pm2_iowrite(0x42, byte);
 387
 388         /* set GPIO 64 to tristate */
 389         word = pci_read_config16(sm_dev, 0x56);
 390         word |= 1 << 7;
 391         pci_write_config16(sm_dev, 0x56, word);
 392
 393         /* set GPIO 64 internal pull-up */
 394         byte = pm2_ioread(0xf0);
 395         byte &= 0xee;
 396         pm2_iowrite(0xf0, byte);
 397
 398         /* set Talert to be active low */
 399         byte = pm_ioread(0x67);
 400         byte &= ~(1 << 5);
 401         pm_iowrite(0x67, byte);
 402
 403         /* set Talert to generate ACPI event */
 404         byte = pm_ioread(0x3c);
 405         byte &= 0xf3;
 406         pm_iowrite(0x3c, byte);
 407
 408         /* set GPM5 to not wake from s5 */
 409         byte = pm_ioread(0x77);
 410         byte &= ~(1 << 5);
 411         pm_iowrite(0x77, byte);
 412 }
 413
 414  /**
 415  * @brief Setup thermal config on SINA Mainboard
 416  *
 417  */
 418
 419 static void set_thermal_config(void)
 420 {
 421         u8 byte, byte2;
 422         u8 cpu_pwm_conf, case_pwm_conf;
 423         device_t sm_dev;
 424         struct fan_control cpu_fan_control, case_fan_control;
 425         const char *name = NULL;
 426
 427
 428         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 429         smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE
 430
 431         if( (name = adt7475_detect()) == NULL ) {
 432                 printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address);
 433                 return;
 434         }
 435         printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address);
 436
 437         cpu_fan_control = cpu_fan_control_defaults;
 438         case_fan_control = case_fan_control_defaults;
 439
 440         if (get_option(&byte, "cpu_fan_control") == CB_CMOS_CHECKSUM_INVALID) {
 441                 printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__);
 442         } else {
 443                 // get all the options needed
 444                 if( get_option(&byte, "cpu_fan_control") == CB_SUCCESS )
 445                         cpu_fan_control.enable = byte ? 1 : 0;
 446
 447                 get_option(&cpu_fan_control.polarity, "cpu_fan_polarity");
 448                 get_option(&cpu_fan_control.t_min, "cpu_t_min");
 449                 get_option(&cpu_fan_control.t_max, "cpu_t_max");
 450                 get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min");
 451                 get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max");
 452
 453                 if( get_option(&byte, "chassis_fan_control") == CB_SUCCESS)
 454                         case_fan_control.enable = byte ? 1 : 0;
 455                 get_option(&case_fan_control.polarity, "chassis_fan_polarity");
 456                 get_option(&case_fan_control.t_min, "chassis_t_min");
 457                 get_option(&case_fan_control.t_max, "chassis_t_max");
 458                 get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min");
 459                 get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max");
 460
 461         }
 462
 463         printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable");
 464         printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high");
 465
 466         printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min));
 467         cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min);
 468
 469         printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max));
 470         cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max);
 471
 472         printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min));
 473         cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min);
 474
 475         printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max));
 476         cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max);
 477
 478         cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max);
 479         printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range);
 480         cpu_fan_control.t_range <<= 4;
 481         cpu_fan_control.t_range |= (4 << 0); // 35.3Hz
 482
 483         printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable");
 484         printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high");
 485
 486         printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min));
 487         case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min);
 488
 489         printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max));
 490         case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max);
 491
 492         printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min));
 493         case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min);
 494
 495         printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max));
 496         case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max);
 497
 498         case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max);
 499         printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range);
 500         case_fan_control.t_range <<= 4;
 501         case_fan_control.t_range |= (4 << 0); // 35.3Hz
 502
 503         cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
 504         case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output
 505         cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5);  // manual control
 506         case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp
 507
 508         /* set adt7475 */
 509
 510         adt7475_write_byte(REG_CONFIG1, 0x04);  // clear register, bit 2 is read only
 511
 512         /* Config Register 6:  */
 513         adt7475_write_byte(REG_CONFIG6, 0x00);
 514         /* Config Register 7 */
 515         adt7475_write_byte(REG_CONFIG7, 0x00);
 516
 517         /* Config Register 5: */
 518         /* set Offset 64 format, enable THERM on Remote 1& Local */
 519         adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60);
 520         /* No offset for remote 1 */
 521         adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00);
 522         /* No offset for local */
 523         adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00);
 524         /* No offset for remote 2 */
 525         adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00);
 526
 527         /* remote 1 low temp limit */
 528         adt7475_write_byte(TEMP_MIN_REG(0), 0x00);
 529         /* remote 1 High temp limit    (90C) */
 530         adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
 531
 532         /* local Low Temp Limit */
 533         adt7475_write_byte(TEMP_MIN_REG(1), 0x00);
 534         /* local High Limit    (90C) */
 535         adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
 536
 537         /*  remote 1 therm temp limit    (95C) */
 538         adt7475_write_byte(TEMP_THERM_REG(0), 0x9f);
 539         /* local therm temp limit    (95C) */
 540         adt7475_write_byte(TEMP_THERM_REG(1), 0x9f);
 541
 542         /* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
 543         adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf);
 544         /* PWM 3 configuration register    Case fan controlled by ADTxxxx temp */
 545         adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
 546
 547         if( cpu_fan_control.enable ) {
 548                 /* PWM 1 minimum duty cycle     (37%) */
 549                 adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min);
 550                 /* PWM 1 Maximum duty cycle    (100%) */
 551                 adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max);
 552                 /*  Remote 1 temperature Tmin     (32C) */
 553                 adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min);
 554                 /* remote 1 Trange            (53C ramp range) */
 555                 adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range);
 556         } else {
 557                 adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max);
 558         }
 559
 560         if( case_fan_control.enable ) {
 561                 /* PWM 2 minimum duty cycle     (37%) */
 562                 adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min);
 563                 /* PWM 2 Maximum Duty Cycle    (100%) */
 564                 adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max);
 565                 /* local temperature Tmin     (32C) */
 566                 adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min);
 567                 /* local Trange            (53C ramp range) */
 568                 adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange
 569                 adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq
 570         } else {
 571                 adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max);
 572         }
 573
 574         /* Config Register 3 - enable smbalert & therm */
 575         adt7475_write_byte(0x78, 0x03);
 576         /* Config Register 4 - enable therm output */
 577         adt7475_write_byte(0x7d, 0x09);
 578         /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */
 579         adt7475_write_byte(0x75, 0x2e);
 580
 581         /* Config Register 1 Set Start bit */
 582         adt7475_write_byte(0x40, 0x05);
 583
 584         /* Read status register to clear any old errors */
 585         byte2 = adt7475_read_byte(0x42);
 586         byte = adt7475_read_byte(0x41);
 587
 588         printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n",
 589                     byte2, byte);
 590
 591 }
 592
 593 static void patch_mmio_nonposted( void )
 594 {
 595         unsigned reg, index;
 596         resource_t rbase, rend;
 597         u32 base, limit;
 598         struct resource *resource;
 599         device_t dev;
 600         device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1));
 601
 602         printk(BIOS_DEBUG,"%s ...\n", __func__);
 603
 604         dev = dev_find_slot(1, PCI_DEVFN(5,0));
 605         // the uma frame buffer
 606         index = 0x10;
 607         resource = probe_resource(dev, index);
 608         if( resource ) {
 609                 // fixup resource nonposted in k8 mmio
 610                 /* Get the base address */
 611                 rbase = (resource->base >> 8) & ~(0xff);
 612                 /* Get the limit (rounded up) */
 613                 rend  = (resource_end(resource) >> 8) & ~(0xff);
 614
 615                 printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend);
 616
 617                 for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
 618                         base = pci_read_config32(k8_f1,reg);
 619                         limit = pci_read_config32(k8_f1,reg+4);
 620                         printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit);
 621                         if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) {
 622                                 limit |= (1 << 7);
 623                                 printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit);
 624                                 pci_write_config32(k8_f1, reg+4, limit);
 625                                 break;
 626                         }
 627                 }
 628                 printk(BIOS_DEBUG, "\n");
 629         }
 630 }
 631
 632 struct {
 633         unsigned int bus;
 634         unsigned int devfn;
 635 } slot[] = {
 636         {0, PCI_DEVFN(0,0)},
 637         {0, PCI_DEVFN(18,0)},
 638         {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)},
 639         {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)},
 640         {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)},
 641         {255,0},
 642 };
 643
 644
 645 unsigned int plx_present = 0;
 646
 647 static void update_subsystemid( device_t dev )
 648 {
 649         int i;
 650
 651         dev->subsystem_vendor = 0x110a;
 652         if( plx_present ){
 653                 dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
 654         } else {
 655                 dev->subsystem_device = 0x4077; // U1P0 = 0x4077
 656         }
 657         printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device );
 658         for( i = 0; slot[i].bus < 255; i++) {
 659                 device_t d;
 660                 d = dev_find_slot(slot[i].bus,slot[i].devfn);
 661                 if( d ) {
 662                         printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device);
 663                         d->subsystem_device = dev->subsystem_device;
 664                 }
 665         }
 666 }
 667
 668 static void detect_hw_variant( device_t dev )
 669 {
 670
 671         device_t nb_dev =0, dev2 = 0;
 672         struct southbridge_amd_rs690_config *cfg;
 673         u32 lc_state, id = 0;
 674
 675         printk(BIOS_INFO, "Scan for PLX device ...\n");
 676         nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 677         if (!nb_dev) {
 678                 die("CAN NOT FIND RS690 DEVICE, HALT!\n");
 679                 /* NOT REACHED */
 680         }
 681
 682         dev2 = dev_find_slot(0, PCI_DEVFN(2, 0));
 683         if (!dev2) {
 684                 die("CAN NOT FIND GFX DEVICE 2, HALT!\n");
 685                 /* NOT REACHED */
 686         }
 687         PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2
 688
 689         mdelay(40);
 690         lc_state = nbpcie_p_read_index(dev2, 0xa5);     /* lc_state */
 691         printk(BIOS_DEBUG, "lc current state=%x\n", lc_state);
 692         /* LC_CURRENT_STATE = bit0-5 */
 693         switch( lc_state & 0x3f ){
 694         case 0x00:
 695         case 0x01:
 696         case 0x02:
 697         case 0x03:
 698         case 0x04:
 699                 printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n");
 700                 break;
 701         case 0x07:
 702         case 0x10:
 703         {
 704                 struct device dummy;
 705                 u32 pci_primary_bus, buses;
 706                 u16 secondary, subordinate;
 707
 708                 printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID));
 709                 // save the existing primary/secondary/subordinate bus number configuration.
 710                 secondary = dev2->bus->secondary;
 711                 subordinate = dev2->bus->subordinate;
 712                 buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS);
 713
 714                 // Configure the bus numbers for this bridge
 715                 // bus number 1 is for internal gfx device, so we start with busnumber 2
 716
 717                 buses &= 0xff000000;
 718                 buses |= ((2 << 8) | (0xff << 16));
 719                 // setup the buses in device 2
 720                 pci_write_config32(dev2,PCI_PRIMARY_BUS, buses);
 721
 722                 // fake a device descriptor for a device behind device 2
 723                 dummy.bus = dev2->bus;
 724                 dummy.bus->secondary = (buses >> 8) & 0xff;
 725                 dummy.bus->subordinate = (buses >> 16) & 0xff;
 726                 dummy.path.type = DEVICE_PATH_PCI;
 727                 dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0
 728
 729                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 730                 /* Have we found something?
 731                  * Some broken boards return 0 if a slot is empty, but
 732                  * the expected answer is 0xffffffff
 733                  */
 734                 if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) {
 735                         printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id);
 736                 } else {
 737                         printk(BIOS_DEBUG, "found device [%x]\n", id);
 738                 }
 739                 // restore changes made for device 2
 740                 dev2->bus->secondary = secondary;
 741                 dev2->bus->subordinate = subordinate;
 742                 pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus);
 743         }
 744                 break;
 745         default:
 746                 break;
 747         }
 748
 749         plx_present = 0;
 750         if( id == PLX_VIDDID ){
 751                 printk(BIOS_INFO, "found PLX device\n");
 752                 plx_present = 1;
 753                 cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
 754                 if( cfg->gfx_tmds ) {
 755                         printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
 756                         cfg->gfx_tmds = 0;
 757                         cfg->gfx_link_width = 4;
 758                 }
 759                 return;
 760         }
 761 }
 762
 763 void smm_lock(void)
 764 {
 765         /* LOCK the SMM memory window and enable normal SMM.
 766          * After running this function, only a full reset can
 767          * make the SMM registers writable again.
 768          */
 769         printk(BIOS_DEBUG, "Locking SMM.\n");
 770         pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69,
 771                         D_LCK | G_SMRAME | A_BASE_SEG);
 772 }
 773
 774  /**
 775  * @brief Init
 776  *
 777  * @param dev - the root device
 778  */
 779
 780 static void mainboard_init(device_t dev)
 781 {
 782 #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 783         INT15_function_extensions int15_func;
 784 #endif
 785
 786         printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
 787                 dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
 788
 789 #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 790         if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS)
 791                 int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
 792         int15_func.regs.func05_TV_standard = TV_MODE_NO;
 793         install_INT15_function_extensions(&int15_func);
 794 #endif
 795         set_thermal_config();
 796         pm_init();
 797         cable_detect();
 798         patch_mmio_nonposted();
 799         smm_lock();
 800 }
 801
 802 /*************************************************
 803 * enable the dedicated function in sina board.
 804 * This function called early than rs690_enable.
 805 *************************************************/
 806 static void mainboard_enable(device_t dev)
 807 {
 808
 809         printk(BIOS_INFO, "%s %s[%x/%x] %s\n",
 810                 dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
 811 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
 812         /* Install custom int15 handler for VGA OPROM */
 813         mainboard_interrupt_handlers(0x15, &int15_handler);
 814 #endif
 815
 816         detect_hw_variant(dev);
 817         update_subsystemid(dev);
 818
 819         dev->ops->init = mainboard_init;  // rest of mainboard init later
 820         dev->ops->acpi_inject_dsdt_generator = mainboard_inject_dsdt;
 821 }
 822
 823 struct chip_operations mainboard_ops = {
 824         .enable_dev = mainboard_enable,
 825 };