util/inteltool/memory.c

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #include <stdio.h>
  18 #include <stdlib.h>
  19 #include <inttypes.h>
  20 #include "inteltool.h"
  21
  22 volatile uint8_t *mchbar;
  23
  24 static void write_mchbar32 (uint32_t addr, uint32_t val)
  25 {
  26         * (volatile uint32_t *) (mchbar + addr) = val;
  27 }
  28
  29 static uint32_t read_mchbar32 (uint32_t addr)
  30 {
  31         return * (volatile uint32_t *) (mchbar + addr);
  32 }
  33
  34 static uint8_t read_mchbar8 (uint32_t addr)
  35 {
  36         return * (volatile uint8_t *) (mchbar + addr);
  37 }
  38
  39 static u16 read_500 (int channel, u16 addr, int split)
  40 {
  41         uint32_t val;
  42         write_mchbar32 (0x500 + (channel << 10), 0);
  43         while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
  44         write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
  45         while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
  46         val = read_mchbar32 (0x508 + (channel << 10));
  47
  48         return val & ((1 << split) - 1);
  49 }
  50
  51 static inline u16 get_lane_offset (int slot, int rank, int lane)
  52 {
  53         return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
  54 }
  55
  56 static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank)
  57 {
  58         const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
  59         return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
  60 }
  61
  62 static void write_1d0 (u32 val, u16 addr, int bits, int flag)
  63 {
  64         write_mchbar32 (0x1d0, 0);
  65         while (read_mchbar32 (0x1d0) & 0x800000);
  66         write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
  67         write_mchbar32 (0x1d0, 0x40000000 | addr);
  68         while (read_mchbar32 (0x1d0) & 0x800000);
  69 }
  70
  71 static u16 read_1d0 (u16 addr, int split)
  72 {
  73         u32 val;
  74         write_mchbar32 (0x1d0, 0);
  75         while (read_mchbar32 (0x1d0) & 0x800000);
  76         write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr));
  77         while (read_mchbar32 (0x1d0) & 0x800000);
  78         val = read_mchbar32 (0x1d8);
  79         write_1d0 (0, 0x33d, 0, 0);
  80         write_1d0 (0, 0x33d, 0, 0);
  81         return val & ((1 << split) - 1);
  82 }
  83
  84 static void dump_timings (void)
  85 {
  86         int channel, slot, rank, lane, i;
  87         printf ("Timings:\n");
  88         for (channel = 0; channel < 2; channel++)
  89                 for (slot = 0; slot < 2; slot++)
  90                         for (rank = 0; rank < 2; rank++) {
  91                                 printf ("channel %d, slot %d, rank %d\n", channel, slot, rank);
  92                                 for (lane = 0; lane < 9; lane++) {
  93                                         printf ("lane %d: ", lane);
  94                                         for (i = 0; i < 4; i++) {
  95                                                 printf ("%x ", read_500 (channel,
  96                                                         get_timing_register_addr (lane, i, slot, rank), 9));
  97                                         }
  98                                 printf ("\n");
  99                                 }
 100                         }
 101
 102         printf ("[178] = %x\n", read_1d0 (0x178, 7));
 103         printf ("[10b] = %x\n", read_1d0 (0x10b, 6));
 104 }
 105
 106
 107 /*
 108  * (G)MCH MMIO Config Space
 109  */
 110 int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file)
 111 {
 112         int i, size = (16 * 1024);
 113         uint64_t mchbar_phys;
 114         struct pci_dev *nb_device6; /* "overflow device" on i865 */
 115         uint16_t pcicmd6;
 116
 117         printf("\n============= MCHBAR ============\n\n");
 118
 119         switch (nb->device_id) {
 120         case PCI_DEVICE_ID_INTEL_82865:
 121                 /*
 122                  * On i865, the memory access enable/disable bit (MCHBAREN on
 123                  * i945/i965) is not in the MCHBAR (i945/i965) register but in
 124                  * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6.
 125                  *
 126                  * The actual base address is in BAR6 on i865 where on
 127                  * i945/i965 the base address is in MCHBAR.
 128                  */
 129                 nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0);  /* Device 6 */
 130                 mchbar_phys = pci_read_long(nb_device6, 0x10);  /* BAR6 */
 131                 pcicmd6 = pci_read_long(nb_device6, 0x04);      /* PCICMD6 */
 132
 133                 /* Try to enable Memory Access Enable (MAE). */
 134                 if (!(pcicmd6 & (1 << 1))) {
 135                         printf("Access to BAR6 is currently disabled, "
 136                                "attempting to enable.\n");
 137                         pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1));
 138                         if (pci_read_long(nb_device6, 0x04) & (1 << 1))
 139                                 printf("Enabled successfully.\n");
 140                         else
 141                                 printf("Enable FAILED!\n");
 142                 }
 143                 mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */
 144                 break;
 145         case PCI_DEVICE_ID_INTEL_82915:
 146         case PCI_DEVICE_ID_INTEL_82945GM:
 147         case PCI_DEVICE_ID_INTEL_82945GSE:
 148         case PCI_DEVICE_ID_INTEL_82945P:
 149         case PCI_DEVICE_ID_INTEL_82975X:
 150                 mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
 151                 break;
 152         case PCI_DEVICE_ID_INTEL_82965PM:
 153         case PCI_DEVICE_ID_INTEL_82Q35:
 154         case PCI_DEVICE_ID_INTEL_82G33:
 155         case PCI_DEVICE_ID_INTEL_82Q33:
 156                 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 157                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 158                 break;
 159         case PCI_DEVICE_ID_INTEL_82946:
 160         case PCI_DEVICE_ID_INTEL_82Q965:
 161         case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 162         case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
 163                 mchbar_phys = pci_read_long(nb, 0x48);
 164
 165                 /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
 166                  * If it isn't, try to set it. This may fail, because there is
 167                  * some bit that locks that bit, and isn't in the public
 168                  * datasheets.
 169                  */
 170
 171                 if(!(mchbar_phys & 1))
 172                 {
 173                         printf("Access to the MCHBAR is currently disabled, "
 174                                    "attempting to enable.\n");
 175                         mchbar_phys |= 0x1;
 176                         pci_write_long(nb, 0x48, mchbar_phys);
 177                         if(pci_read_long(nb, 0x48) & 1)
 178                                 printf("Enabled successfully.\n");
 179                         else
 180                                 printf("Enable FAILED!\n");
 181                 }
 182                 mchbar_phys &= 0xfffffffe;
 183                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 184                 break;
 185         case PCI_DEVICE_ID_INTEL_82443LX:
 186         case PCI_DEVICE_ID_INTEL_82443BX:
 187         case PCI_DEVICE_ID_INTEL_82810:
 188         case PCI_DEVICE_ID_INTEL_82810E_DC:
 189         case PCI_DEVICE_ID_INTEL_82810_DC:
 190         case PCI_DEVICE_ID_INTEL_82830M:
 191                 printf("This northbridge does not have MCHBAR.\n");
 192                 return 1;
 193         case PCI_DEVICE_ID_INTEL_82XX4X:
 194         case PCI_DEVICE_ID_INTEL_82Q45:
 195         case PCI_DEVICE_ID_INTEL_82G45:
 196         case PCI_DEVICE_ID_INTEL_82G41:
 197         case PCI_DEVICE_ID_INTEL_82B43:
 198         case PCI_DEVICE_ID_INTEL_82B43_2:
 199         case PCI_DEVICE_ID_INTEL_82X38:
 200         case PCI_DEVICE_ID_INTEL_32X0:
 201                 mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
 202                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 203                 break;
 204         case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
 205                 mchbar_phys = pci_read_long(nb, 0x48);
 206                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 207                 mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
 208                 break;
 209         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
 210         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
 211         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
 212         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
 213         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
 214         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
 215         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
 216         case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
 217         case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
 218         case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
 219         case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
 220         case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
 221         case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2:
 222         case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
 223         case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
 224         case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E:
 225         case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
 226         case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
 227         case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
 228         case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
 229         case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3:
 230                 mchbar_phys = pci_read_long(nb, 0x48);
 231                 mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
 232                 mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
 233                 size = 32768;
 234                 break;
 235         default:
 236                 printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
 237                 return 1;
 238         }
 239
 240         mchbar = map_physical(mchbar_phys, size);
 241
 242         if (mchbar == NULL) {
 243                 if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
 244                         perror("Error mapping BAR6");
 245                 else
 246                         perror("Error mapping MCHBAR");
 247                 exit(1);
 248         }
 249
 250         if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
 251                 printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
 252         else
 253                 printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
 254
 255         for (i = 0; i < size; i += 4) {
 256                 if (*(uint32_t *)(mchbar + i))
 257                         printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
 258         }
 259
 260         switch (nb->device_id)
 261         {
 262         case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
 263                 printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
 264                 dump_timings ();
 265                 if (dump_spd_file != NULL)
 266                         printf("\nCreating a memory timings file is not supported on this chipset.\n");
 267                 break;
 268         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
 269         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
 270         case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
 271         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
 272         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
 273         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
 274         case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
 275                 ivybridge_dump_timings(dump_spd_file);
 276                 break;
 277         default:
 278                 if (dump_spd_file != NULL)
 279                         printf("\nCreating a memory timings file is not supported on this chipset.\n");
 280         }
 281         unmap_physical((void *)mchbar, size);
 282         return 0;
 283 }