2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
21 mainmenu "coreboot configuration"
28 This allows you to select certain advanced configuration options.
30 Warning: Only enable this option if you really know what you are
31 doing! You have been warned!
34 string "Local version string"
36 Append an extra string to the end of the coreboot version.
38 This can be useful if, for instance, you want to append the
39 respective board's hostname or some other identifying string to
40 the coreboot version number, so that you can easily distinguish
41 boot logs of different boards from each other.
44 string "CBFS prefix to use"
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
50 config COMMON_CBFS_SPI_WRAPPER
56 Use common wrapper to interface CBFS to SPI bootrom.
58 config MULTIPLE_CBFS_INSTANCES
59 bool "Multiple CBFS instances in the bootrom"
63 Account for the firmware image containing more than one CBFS
64 instance. Locations of instances are known at build time and are
65 communicated between coreboot stages to make sure the next stage is
66 loaded from the appropriate instance.
69 prompt "Compiler to use"
72 This option allows you to select the compiler used for building
78 Use the GNU Compiler Collection (GCC) to build coreboot.
80 For details see http://gcc.gnu.org.
82 config COMPILER_LLVM_CLANG
85 Use LLVM/clang to build coreboot.
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
116 Enable this option if you are working on the flashmap descriptor
117 parser and made changes to fmd_scanner.l or fmd_parser.y.
119 Otherwise, say N to use the provided pregenerated scanner/parser.
121 config SCONFIG_GENPARSER
122 bool "Generate SCONFIG parser using flex and bison"
126 Enable this option if you are working on the sconfig device tree
127 parser and made changes to sconfig.l or sconfig.y.
129 Otherwise, say N to use the provided pregenerated scanner/parser.
131 config USE_OPTION_TABLE
132 bool "Use CMOS for configuration values"
134 depends on HAVE_OPTION_TABLE
136 Enable this option if coreboot shall read options from the "CMOS"
137 NVRAM instead of using hard-coded values.
139 config STATIC_OPTION_TABLE
140 bool "Load default configuration values into CMOS on each boot"
142 depends on USE_OPTION_TABLE
144 Enable this option to reset "CMOS" NVRAM values to default on
145 every boot. Use this if you want the NVRAM configuration to
146 never be modified from its default values.
148 config UNCOMPRESSED_RAMSTAGE
152 config COMPRESS_RAMSTAGE
153 bool "Compress ramstage with LZMA"
154 default y if !UNCOMPRESSED_RAMSTAGE
157 Compress ramstage to save memory in the flash image. Note
158 that decompression might slow down booting if the boot flash
159 is connected through a slow link (i.e. SPI).
161 config INCLUDE_CONFIG_FILE
162 bool "Include the coreboot .config file into the ROM image"
165 Include the .config file that was used to compile coreboot
166 in the (CBFS) ROM image. This is useful if you want to know which
167 options were used to build a specific coreboot.rom image.
169 Saying Y here will increase the image size by 2-3KB.
171 You can use the following command to easily list the options:
173 grep -a CONFIG_ coreboot.rom
175 Alternatively, you can also use cbfstool to print the image
176 contents (including the raw 'config' item we're looking for).
180 $ cbfstool coreboot.rom print
181 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
185 Name Offset Type Size
186 cmos_layout.bin 0x0 cmos layout 1159
187 fallback/romstage 0x4c0 stage 339756
188 fallback/ramstage 0x53440 stage 186664
189 fallback/payload 0x80dc0 payload 51526
190 config 0x8d740 raw 3324
191 (empty) 0x8e480 null 3610440
193 config EARLY_CBMEM_INIT
194 def_bool !LATE_CBMEM_INIT
196 config COLLECT_TIMESTAMPS
197 bool "Create a table of timestamps collected during boot"
200 Make coreboot create a table of timer-ID/timer-value pairs to
201 allow measuring time spent at different phases of the boot process.
204 bool "Allow use of binary-only repository"
207 This draws in the blobs repository, which contains binary files that
208 might be required for some chipsets or boards.
209 This flag ensures that a "Free" option remains available for users.
212 bool "Code coverage support"
213 depends on COMPILER_GCC
216 Add code coverage support for coreboot. This will store code
217 coverage information in CBMEM for extraction from user space.
220 config RELOCATABLE_MODULES
224 If RELOCATABLE_MODULES is selected then support is enabled for
225 building relocatable modules in the RAM stage. Those modules can be
226 loaded anywhere and all the relocations are handled automatically.
228 config RELOCATABLE_RAMSTAGE
229 depends on EARLY_CBMEM_INIT
230 bool "Build the ramstage to be relocatable in 32-bit address space."
232 select RELOCATABLE_MODULES
234 The reloctable ramstage support allows for the ramstage to be built
235 as a relocatable module. The stage loader can identify a place
236 out of the OS way so that copying memory is unnecessary during an S3
237 wake. When selecting this option the romstage is responsible for
238 determing a stack location to use for loading the ramstage.
240 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
241 depends on RELOCATABLE_RAMSTAGE
242 bool "Cache the relocated ramstage outside of cbmem."
245 The relocated ramstage is saved in an area specified by the
246 by the board and/or chipset.
248 config FLASHMAP_OFFSET
249 hex "Flash Map Offset"
250 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
251 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
252 default CBFS_SIZE if !ARCH_X86
255 Offset of flash map in firmware image
258 prompt "Bootblock behaviour"
259 default BOOTBLOCK_SIMPLE
261 config BOOTBLOCK_SIMPLE
262 bool "Always load fallback"
264 config BOOTBLOCK_NORMAL
265 bool "Switch to normal if CMOS says so"
269 config BOOTBLOCK_SOURCE
271 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
272 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
274 config SKIP_MAX_REBOOT_CNT_CLEAR
275 bool "Do not clear reboot count after successful boot"
279 Do not clear the reboot count immediately after successful boot.
280 Set to allow the payload to control normal/fallback image recovery.
283 bool "Update existing coreboot.rom image"
286 If this option is enabled, no new coreboot.rom file
287 is created. Instead it is expected that there already
288 is a suitable file for further processing.
289 The bootblock will not be modified.
291 config GENERIC_GPIO_LIB
295 If enabled, compile the generic GPIO library. A "generic" GPIO
296 implies configurability usually found on SoCs, particularly the
297 ability to control internal pull resistors.
303 Mainboards that can read a board ID from the hardware straps
304 (ie. GPIO) select this configuration option.
306 config BOARD_ID_MANUAL
307 bool "Add board ID file to CBFS"
309 depends on !BOARD_ID_AUTO
311 If you want to maintain a board ID, but the hardware does not
312 have straps to automatically determine the ID, you can say Y
313 here and add a file named 'board_id' to CBFS. If you don't know
314 what this is about, say N.
316 config BOARD_ID_STRING
319 depends on BOARD_ID_MANUAL
321 This string is placed in the 'board_id' CBFS file for indicating
324 config RAM_CODE_SUPPORT
325 bool "Discover RAM configuration code and store it in coreboot table"
328 If enabled, coreboot discovers RAM configuration (value obtained by
329 reading board straps) and stores it in coreboot table.
333 source "src/acpi/Kconfig"
337 source "src/mainboard/Kconfig"
340 hex "Size of CBFS filesystem in ROM"
341 default 0x100000 if HAVE_INTEL_FIRMWARE || \
342 NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
343 NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \
344 NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \
345 NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
349 This is the part of the ROM actually managed by CBFS, located at the
350 end of the ROM (passed through cbfstool -o) on x86 and at at the start
351 of the ROM (passed through cbfstool -s) everywhere else. It defaults
352 to span the whole ROM on all but Intel systems that use an Intel Firmware
353 Descriptor. It can be overridden to make coreboot live alongside other
354 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
359 config SYSTEM_TYPE_LAPTOP
366 source "src/soc/*/*/Kconfig"
368 source "src/cpu/Kconfig"
369 comment "Northbridge"
370 source "src/northbridge/*/*/Kconfig"
371 comment "Southbridge"
372 source "src/southbridge/*/*/Kconfig"
374 source "src/superio/*/Kconfig"
375 comment "Embedded Controllers"
376 source "src/ec/acpi/Kconfig"
377 source "src/ec/*/*/Kconfig"
378 source "src/drivers/intel/fsp1_0/Kconfig"
380 source "src/southbridge/intel/common/firmware/Kconfig"
381 source "src/vendorcode/*/Kconfig"
383 source "src/arch/*/Kconfig"
387 source "src/device/Kconfig"
389 menu "Generic Drivers"
390 source "src/drivers/*/Kconfig"
400 select LPC_TPM if ARCH_X86
401 select I2C_TPM if ARCH_ARM
402 select I2C_TPM if ARCH_ARM64
404 Enable this option to enable TPM support in coreboot.
419 default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS)
426 config MMCONF_SUPPORT_DEFAULT
430 config MMCONF_SUPPORT
434 config BOOTMODE_STRAPS
438 source "src/console/Kconfig"
440 config HAVE_ACPI_RESUME
444 config HAVE_HARD_RESET
448 This variable specifies whether a given board has a hard_reset
449 function, no matter if it's provided by board code or chipset code.
451 config HAVE_MONOTONIC_TIMER
454 The board/chipset provides a monotonic timer.
456 config GENERIC_UDELAY
458 depends on HAVE_MONOTONIC_TIMER
460 The board/chipset uses a generic udelay function utilizing the
465 depends on HAVE_MONOTONIC_TIMER
467 Provide a timer queue for performing time-based callbacks.
469 config COOP_MULTITASKING
471 depends on TIMER_QUEUE && ARCH_X86
473 Cooperative multitasking allows callbacks to be multiplexed on the
474 main thread of ramstage. With this enabled it allows for multiple
475 execution paths to take place when they have udelay() calls within
481 depends on COOP_MULTITASKING
483 How many execution threads to cooperatively multitask with.
485 config HAVE_OPTION_TABLE
489 This variable specifies whether a given board has a cmos.layout
490 file containing NVRAM/CMOS bit definitions.
491 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
497 config HAVE_SMI_HANDLER
501 config PCI_IO_CFG_EXT
509 config CACHE_ROM_SIZE_OVERRIDE
513 # TODO: Can probably be removed once all chipsets have kconfig options for it.
518 config USE_WATCHDOG_ON_BOOT
526 Build board-specific VGA code.
532 Enable Unified Memory Architecture for graphics.
534 config HAVE_ACPI_TABLES
537 This variable specifies whether a given board has ACPI table support.
538 It is usually set in mainboard/*/Kconfig.
543 This variable specifies whether a given board has MP table support.
544 It is usually set in mainboard/*/Kconfig.
545 Whether or not the MP table is actually generated by coreboot
546 is configurable by the user via GENERATE_MP_TABLE.
548 config HAVE_PIRQ_TABLE
551 This variable specifies whether a given board has PIRQ table support.
552 It is usually set in mainboard/*/Kconfig.
553 Whether or not the PIRQ table is actually generated by coreboot
554 is configurable by the user via GENERATE_PIRQ_TABLE.
556 config MAX_PIRQ_LINKS
560 This variable specifies the number of PIRQ interrupt links which are
561 routable. On most chipsets, this is 4, INTA through INTD. Some
562 chipsets offer more than four links, commonly up to INTH. They may
563 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
564 table specifies links greater than 4, pirq_route_irqs will not
565 function properly, unless this variable is correctly set.
571 #These Options are here to avoid "undefined" warnings.
572 #The actual selection and help texts are in the following menu.
576 config GENERATE_MP_TABLE
577 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
579 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
581 Generate an MP table (conforming to the Intel MultiProcessor
582 specification 1.4) for this board.
586 config GENERATE_PIRQ_TABLE
587 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
589 default HAVE_PIRQ_TABLE
591 Generate a PIRQ table for this board.
595 config GENERATE_SMBIOS_TABLES
597 bool "Generate SMBIOS tables"
600 Generate SMBIOS tables for this board.
604 config SMBIOS_PROVIDED_BY_MOBO
608 config MAINBOARD_SERIAL_NUMBER
609 string "SMBIOS Serial Number"
610 depends on GENERATE_SMBIOS_TABLES
611 depends on !SMBIOS_PROVIDED_BY_MOBO
614 The Serial Number to store in SMBIOS structures.
616 config MAINBOARD_VERSION
617 string "SMBIOS Version Number"
618 depends on GENERATE_SMBIOS_TABLES
619 depends on !SMBIOS_PROVIDED_BY_MOBO
622 The Version Number to store in SMBIOS structures.
624 config MAINBOARD_SMBIOS_MANUFACTURER
625 string "SMBIOS Manufacturer"
626 depends on GENERATE_SMBIOS_TABLES
627 depends on !SMBIOS_PROVIDED_BY_MOBO
628 default MAINBOARD_VENDOR
630 Override the default Manufacturer stored in SMBIOS structures.
632 config MAINBOARD_SMBIOS_PRODUCT_NAME
633 string "SMBIOS Product name"
634 depends on GENERATE_SMBIOS_TABLES
635 depends on !SMBIOS_PROVIDED_BY_MOBO
636 default MAINBOARD_PART_NUMBER
638 Override the default Product name stored in SMBIOS structures.
645 prompt "Add a payload"
646 default PAYLOAD_NONE if !ARCH_X86
647 default PAYLOAD_SEABIOS if ARCH_X86
652 Select this option if you want to create an "empty" coreboot
653 ROM image for a certain mainboard, i.e. a coreboot ROM image
654 which does not yet contain a payload.
656 For such an image to be useful, you have to use 'cbfstool'
657 to add a payload to the ROM image later.
660 bool "An ELF executable payload"
662 Select this option if you have a payload image (an ELF file)
663 which coreboot should run as soon as the basic hardware
664 initialization is completed.
666 You will be able to specify the location and file name of the
670 bool "A Linux payload"
672 Select this option if you have a Linux bzImage which coreboot
673 should run as soon as the basic hardware initialization
676 You will be able to specify the location and file name of the
679 config PAYLOAD_SEABIOS
683 Select this option if you want to build a coreboot image
684 with a SeaBIOS payload. If you don't know what this is
685 about, just leave it enabled.
687 See http://coreboot.org/Payloads for more information.
692 Select this option if you want to build a coreboot image
693 with a FILO payload. If you don't know what this is
694 about, just leave it enabled.
696 See http://coreboot.org/Payloads for more information.
701 Select this option if you want to build a coreboot image
702 with a GRUB2 payload. If you don't know what this is
703 about, just leave it enabled.
705 See http://coreboot.org/Payloads for more information.
707 config PAYLOAD_TIANOCORE
710 Select this option if you want to build a coreboot image
711 with a Tiano Core payload. If you don't know what this is
712 about, just leave it enabled.
714 See http://coreboot.org/Payloads for more information.
719 prompt "SeaBIOS version"
720 default SEABIOS_STABLE
721 depends on PAYLOAD_SEABIOS
723 config SEABIOS_STABLE
726 Stable SeaBIOS version
727 config SEABIOS_MASTER
730 Newest SeaBIOS version
734 config SEABIOS_PS2_TIMEOUT
735 prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
740 Some PS/2 keyboard controllers don't respond to commands immediately
741 after powering on. This specifies how long SeaBIOS will wait for the
742 keyboard controller to become ready before giving up.
744 config SEABIOS_THREAD_OPTIONROMS
745 prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS
749 Allow hardware init to run in parallel with optionrom execution.
751 This can reduce boot time, but can cause some timing
752 variations during option ROM code execution. It is not
753 known if all option ROMs will behave properly with this option.
755 config SEABIOS_MALLOC_UPPERMEMORY
758 depends on PAYLOAD_SEABIOS
760 Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
761 "low memory" allocations. If this is not selected, the memory is
762 instead allocated from the "9-segment" (0x90000-0xa0000).
763 This is not typically needed, but may be required on some platforms
764 to allow USB and SATA buffers to be written correctly by the
765 hardware. In general, if this is desired, the option will be
766 set to 'N' by the chipset Kconfig.
768 config SEABIOS_VGA_COREBOOT
769 prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS
771 depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG)
774 Coreboot can initialize the GPU of some mainboards.
776 After initializing the GPU, the information about it can be passed to the payload.
777 Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
780 prompt "GRUB2 version"
782 depends on PAYLOAD_GRUB2
792 prompt "FILO version"
794 depends on PAYLOAD_FILO
809 string "Payload path and filename"
810 depends on PAYLOAD_ELF
811 default "payload.elf"
813 The path and filename of the ELF executable file to use as payload.
816 string "Linux path and filename"
817 depends on PAYLOAD_LINUX
820 The path and filename of the bzImage kernel to use as payload.
823 depends on PAYLOAD_SEABIOS
824 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
826 config PAYLOAD_VGABIOS_FILE
828 depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT
829 default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
832 depends on PAYLOAD_FILO
833 default "payloads/external/FILO/filo/build/filo.elf"
836 depends on PAYLOAD_GRUB2
837 default "payloads/external/GRUB2/grub2/build/default_payload.elf"
840 string "Tianocore firmware volume"
841 depends on PAYLOAD_TIANOCORE
842 default "COREBOOT.fd"
844 The result of a corebootPkg build
846 # TODO: Defined if no payload? Breaks build?
847 config COMPRESSED_PAYLOAD_LZMA
848 bool "Use LZMA compression for payloads"
850 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
852 In order to reduce the size payloads take up in the ROM chip
853 coreboot can compress them using the LZMA algorithm.
855 config LINUX_COMMAND_LINE
856 string "Linux command line"
857 depends on PAYLOAD_LINUX
860 A command line to add to the Linux kernel.
863 string "Linux initrd"
864 depends on PAYLOAD_LINUX
867 An initrd image to add to the Linux kernel.
873 # TODO: Better help text and detailed instructions.
875 bool "GDB debugging support"
878 If enabled, you will be able to set breakpoints for gdb debugging.
879 See src/arch/x86/lib/c_start.S for details.
882 bool "Wait for a GDB connection"
886 If enabled, coreboot will wait for a GDB connection.
889 bool "Halt when hitting a BUG() or assertion error"
892 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
895 bool "Output verbose CBFS debug messages"
898 This option enables additional CBFS related debug messages.
900 config HAVE_DEBUG_RAM_SETUP
903 config DEBUG_RAM_SETUP
904 bool "Output verbose RAM init debug messages"
906 depends on HAVE_DEBUG_RAM_SETUP
908 This option enables additional RAM init related debug messages.
909 It is recommended to enable this when debugging issues on your
910 board which might be RAM init related.
912 Note: This option will increase the size of the coreboot image.
916 config HAVE_DEBUG_CAR
921 depends on HAVE_DEBUG_CAR
923 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
924 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
925 # printk(BIOS_DEBUG, ...) calls.
927 bool "Output verbose Cache-as-RAM debug messages"
929 depends on HAVE_DEBUG_CAR
931 This option enables additional CAR related debug messages.
935 bool "Check PIRQ table consistency"
937 depends on GENERATE_PIRQ_TABLE
941 config HAVE_DEBUG_SMBUS
945 bool "Output verbose SMBus debug messages"
947 depends on HAVE_DEBUG_SMBUS
949 This option enables additional SMBus (and SPD) debug messages.
951 Note: This option will increase the size of the coreboot image.
956 bool "Output verbose SMI debug messages"
958 depends on HAVE_SMI_HANDLER
960 This option enables additional SMI related debug messages.
962 Note: This option will increase the size of the coreboot image.
966 config DEBUG_SMM_RELOCATION
967 bool "Debug SMM relocation code"
969 depends on HAVE_SMI_HANDLER
971 This option enables additional SMM handler relocation related
974 Note: This option will increase the size of the coreboot image.
978 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
979 # printk(BIOS_DEBUG, ...) calls.
981 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
985 This option enables additional malloc related debug messages.
987 Note: This option will increase the size of the coreboot image.
991 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
992 # printk(BIOS_DEBUG, ...) calls.
994 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
998 This option enables additional ACPI related debug messages.
1000 Note: This option will slightly increase the size of the coreboot image.
1004 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
1005 # printk(BIOS_DEBUG, ...) calls.
1006 config REALMODE_DEBUG
1007 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
1010 depends on PCI_OPTION_ROM_RUN_REALMODE
1012 This option enables additional x86emu related debug messages.
1014 Note: This option will increase the time to emulate a ROM.
1019 bool "Output verbose x86emu debug messages"
1021 depends on PCI_OPTION_ROM_RUN_YABEL
1023 This option enables additional x86emu related debug messages.
1025 Note: This option will increase the size of the coreboot image.
1029 config X86EMU_DEBUG_JMP
1030 bool "Trace JMP/RETF"
1032 depends on X86EMU_DEBUG
1034 Print information about JMP and RETF opcodes from x86emu.
1036 Note: This option will increase the size of the coreboot image.
1040 config X86EMU_DEBUG_TRACE
1041 bool "Trace all opcodes"
1043 depends on X86EMU_DEBUG
1045 Print _all_ opcodes that are executed by x86emu.
1047 WARNING: This will produce a LOT of output and take a long time.
1049 Note: This option will increase the size of the coreboot image.
1053 config X86EMU_DEBUG_PNP
1054 bool "Log Plug&Play accesses"
1056 depends on X86EMU_DEBUG
1058 Print Plug And Play accesses made by option ROMs.
1060 Note: This option will increase the size of the coreboot image.
1064 config X86EMU_DEBUG_DISK
1067 depends on X86EMU_DEBUG
1069 Print Disk I/O related messages.
1071 Note: This option will increase the size of the coreboot image.
1075 config X86EMU_DEBUG_PMM
1078 depends on X86EMU_DEBUG
1080 Print messages related to POST Memory Manager (PMM).
1082 Note: This option will increase the size of the coreboot image.
1087 config X86EMU_DEBUG_VBE
1088 bool "Debug VESA BIOS Extensions"
1090 depends on X86EMU_DEBUG
1092 Print messages related to VESA BIOS Extension (VBE) functions.
1094 Note: This option will increase the size of the coreboot image.
1098 config X86EMU_DEBUG_INT10
1099 bool "Redirect INT10 output to console"
1101 depends on X86EMU_DEBUG
1103 Let INT10 (i.e. character output) calls print messages to debug output.
1105 Note: This option will increase the size of the coreboot image.
1109 config X86EMU_DEBUG_INTERRUPTS
1110 bool "Log intXX calls"
1112 depends on X86EMU_DEBUG
1114 Print messages related to interrupt handling.
1116 Note: This option will increase the size of the coreboot image.
1120 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1121 bool "Log special memory accesses"
1123 depends on X86EMU_DEBUG
1125 Print messages related to accesses to certain areas of the virtual
1126 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1128 Note: This option will increase the size of the coreboot image.
1132 config X86EMU_DEBUG_MEM
1133 bool "Log all memory accesses"
1135 depends on X86EMU_DEBUG
1137 Print memory accesses made by option ROM.
1138 Note: This also includes accesses to fetch instructions.
1140 Note: This option will increase the size of the coreboot image.
1144 config X86EMU_DEBUG_IO
1145 bool "Log IO accesses"
1147 depends on X86EMU_DEBUG
1149 Print I/O accesses made by option ROM.
1151 Note: This option will increase the size of the coreboot image.
1155 config X86EMU_DEBUG_TIMINGS
1156 bool "Output timing information"
1158 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1160 Print timing information needed by i915tool.
1165 bool "Output verbose TPM debug messages"
1169 This option enables additional TPM related debug messages.
1171 config DEBUG_SPI_FLASH
1172 bool "Output verbose SPI flash debug messages"
1174 depends on SPI_FLASH
1176 This option enables additional SPI flash related debug messages.
1178 config DEBUG_USBDEBUG
1179 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1183 This option enables additional USB 2.0 debug dongle related messages.
1185 Select this to debug the connection of usbdebug dongle. Note that
1186 you need some other working console to receive the messages.
1188 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1189 # Only visible with the right southbridge and loglevel.
1190 config DEBUG_INTEL_ME
1191 bool "Verbose logging for Intel Management Engine"
1194 Enable verbose logging for Intel Management Engine driver that
1195 is present on Intel 6-series chipsets.
1199 bool "Trace function calls"
1202 If enabled, every function will print information to console once
1203 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1204 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1205 of calling function. Please note some printk releated functions
1206 are omitted from trace to have good looking console dumps.
1208 config DEBUG_COVERAGE
1209 bool "Debug code coverage"
1213 If enabled, the code coverage hooks in coreboot will output some
1214 information about the coverage data that is dumped.
1218 # These probably belong somewhere else, but they are needed somewhere.
1219 config ENABLE_APIC_EXT_ID
1223 config WARNINGS_ARE_ERRORS
1227 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1228 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1229 # mutually exclusive. One of these options must be selected in the
1230 # mainboard Kconfig if the chipset supports enabling and disabling of
1231 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1232 # in mainboard/Kconfig to know if the button should be enabled or not.
1234 config POWER_BUTTON_DEFAULT_ENABLE
1237 Select when the board has a power button which can optionally be
1238 disabled by the user.
1240 config POWER_BUTTON_DEFAULT_DISABLE
1243 Select when the board has a power button which can optionally be
1244 enabled by the user, e.g. when the board ships with a jumper over
1245 the power switch contacts.
1247 config POWER_BUTTON_FORCE_ENABLE
1250 Select when the board requires that the power button is always
1253 config POWER_BUTTON_FORCE_DISABLE
1256 Select when the board requires that the power button is always
1257 disabled, e.g. when it has been hardwired to ground.
1259 config POWER_BUTTON_IS_OPTIONAL
1261 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1262 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1264 Internal option that controls ENABLE_POWER_BUTTON visibility.
1270 Internal option that controls whether we compile in register scripts.
1272 config MAX_REBOOT_CNT
1276 Internal option that sets the maximum number of bootblock executions allowed
1277 with the normal image enabled before assuming the normal image is defective
1278 and switching to the fallback image.