2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
24 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <cpu/x86/lapic.h>
28 #include <romstage_handoff.h>
29 #include <console/console.h>
30 #include <cpu/x86/bist.h>
31 #include <cpu/intel/romstage.h>
32 #include <ec/acpi/ec.h>
33 #include <timestamp.h>
34 #include <arch/acpi.h>
37 #include <arch/early_variables.h>
38 #include <southbridge/intel/ibexpeak/pch.h>
39 #include <southbridge/intel/common/gpio.h>
40 #include <northbridge/intel/nehalem/nehalem.h>
42 #include <northbridge/intel/nehalem/raminit.h>
43 #include <southbridge/intel/ibexpeak/me.h>
45 static void pch_enable_lpc(void)
47 /* EC Decode Range Port60/64, Port62/66 */
48 /* Enable EC, PS/2 Keyboard/Mouse */
49 pci_write_config16(PCH_LPC_DEV
, LPC_EN
,
50 CNF2_LPC_EN
| CNF1_LPC_EN
| MC_LPC_EN
| KBC_LPC_EN
|
51 COMA_LPC_EN
| GAMEL_LPC_EN
);
53 pci_write_config32(PCH_LPC_DEV
, LPC_GEN1_DEC
, 0x7c1601);
54 pci_write_config32(PCH_LPC_DEV
, LPC_GEN2_DEC
, 0xc15e1);
55 pci_write_config32(PCH_LPC_DEV
, LPC_GEN3_DEC
, 0x1c1681);
56 pci_write_config32(PCH_LPC_DEV
, LPC_GEN4_DEC
, (0x68 & ~3) | 0x00040001);
58 pci_write_config16(PCH_LPC_DEV
, LPC_IO_DEC
, 0x10);
60 pci_write_config32(PCH_LPC_DEV
, 0xd0, 0x0);
61 pci_write_config32(PCH_LPC_DEV
, 0xdc, 0x8);
63 pci_write_config8(PCH_LPC_DEV
, GEN_PMCON_3
,
64 (pci_read_config8(PCH_LPC_DEV
, GEN_PMCON_3
) & ~2) | 1);
66 pci_write_config32(PCH_LPC_DEV
, ETR3
,
67 pci_read_config32(PCH_LPC_DEV
, ETR3
) & ~ETR3_CF9GR
);
70 static void rcba_config(void)
72 southbridge_configure_default_intmap();
74 static const u32 rcba_dump3
[] = {
75 /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
76 /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
77 /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
78 /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
79 /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
80 /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
81 /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
82 /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
83 /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
84 /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
85 /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
86 /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
87 /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
88 /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
89 /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
90 /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
91 /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f,
92 /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
93 /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
94 /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
95 /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
96 /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
97 /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
98 /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
99 /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
100 /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
101 /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
102 /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
103 /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
104 /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
105 /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
106 /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
107 /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
108 /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
109 /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
110 /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
111 /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
112 /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
113 /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
114 /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
115 /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
116 /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
117 /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
118 /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
119 /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
120 /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
121 /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
122 /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
123 /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
124 /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
125 /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
126 /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
127 /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
128 /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
129 /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
130 /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
131 /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
132 /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
133 /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
134 /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
135 /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
136 /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
137 /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
138 /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
139 /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
140 /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
143 for (i
= 0; i
< sizeof(rcba_dump3
) / 4; i
++) {
144 RCBA32(4 * i
+ 0x3310) = rcba_dump3
[i
];
145 (void)RCBA32(4 * i
+ 0x3310);
149 static inline void write_acpi32(u32 addr
, u32 val
)
151 outl(val
, DEFAULT_PMBASE
| addr
);
154 static inline void write_acpi16(u32 addr
, u16 val
)
156 outw(val
, DEFAULT_PMBASE
| addr
);
159 static inline u32
read_acpi32(u32 addr
)
161 return inl(DEFAULT_PMBASE
| addr
);
164 static void set_fsb_frequency(void)
168 smbus_block_read(0x69, 0, 5, block
);
170 block
[1] = fsbfreq
>> 8;
172 smbus_block_write(0x69, 0, 5, block
);
175 void mainboard_romstage_entry(unsigned long bist
)
179 const u8 spd_addrmap
[4] = { 0x50, 0, 0x51, 0 };
181 timestamp_init(timestamp_get());
183 timestamp_add_now(TS_START_ROMSTAGE
);
188 nehalem_early_initialization(NEHALEM_MOBILE
);
192 /* Enable USB Power. We need to do it early for usbdebug to work. */
196 pci_write_config32(PCH_LPC_DEV
, GPIO_BASE
, DEFAULT_GPIOBASE
| 1);
197 pci_write_config8(PCH_LPC_DEV
, GPIO_CNTL
, 0x10);
199 setup_pch_gpios(&mainboard_gpio_map
);
202 /* This should probably go away. Until now it is required
203 * and mainboard specific
209 /* Halt if there was a built in self test failure */
210 report_bist_failure(bist
);
213 reg32
= inl(DEFAULT_PMBASE
+ 0x04);
214 printk(BIOS_DEBUG
, "PM1_CNT: %08x\n", reg32
);
215 if (((reg32
>> 10) & 7) == 5) {
217 reg8
= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
218 printk(BIOS_DEBUG
, "a2: %02x\n", reg8
);
219 if (!(reg8
& 0x20)) {
220 outl(reg32
& ~(7 << 10), DEFAULT_PMBASE
+ 0x04);
221 printk(BIOS_DEBUG
, "Bad resume from S3 detected.\n");
223 if (acpi_s3_resume_allowed()) {
224 printk(BIOS_DEBUG
, "Resume from S3 detected.\n");
228 "Resume from S3 detected, but disabled.\n");
236 outb((inb(DEFAULT_GPIOBASE
| 0x3a) & ~0x2) | 0x20,
237 DEFAULT_GPIOBASE
| 0x3a);
239 outb(inb(0x15ee) & 0x70, 0x15ee);
241 write_acpi16(0x2, 0x0);
242 write_acpi32(0x28, 0x0);
243 write_acpi32(0x2c, 0x0);
248 write_acpi16(0x0, 0x900);
249 write_acpi32(0x20, 0xffff7ffe);
250 write_acpi32(0x34, 0x56974);
251 pci_write_config8(PCH_LPC_DEV
, GEN_PMCON_3
,
252 pci_read_config8(PCH_LPC_DEV
, GEN_PMCON_3
) | 2);
255 early_thermal_init();
257 timestamp_add_now(TS_BEFORE_INITRAM
);
259 chipset_init(s3resume
);
263 raminit(s3resume
, spd_addrmap
);
265 timestamp_add_now(TS_AFTER_INITRAM
);
267 intel_early_me_status();
270 /* Clear SLP_TYPE. This will break stage2 but
271 * we care for that when we get there.
273 reg32
= inl(DEFAULT_PMBASE
+ 0x04);
274 outl(reg32
& ~(7 << 10), DEFAULT_PMBASE
+ 0x04);
277 romstage_handoff_init(s3resume
);