3 List of maintainers and how to submit coreboot changes
5 Please try to follow the guidelines below. This will make things
6 easier on the maintainers. Not all of these guidelines matter for every
7 trivial patch so apply some common sense.
9 1. Always _test_ your changes, however small, on at least 1 or
10 2 people, preferably many more.
12 2. Try to release a few ALPHA test versions to gerrit. Announce
13 them onto the coreboot mailing list and IRC channel and await
14 results. This is especially important on coreboot core changes,
15 but also for device drivers, because often that's the only way
16 you will find things like the fact revision 3 chipset needs
17 a magic fix you didn't know about, or some clown changed the
18 chips on a board and not its name. (Don't laugh!)
20 3. Make sure your changes compile correctly in multiple
21 configurations. In particular check that changes work for all
22 boards in the tree (use abuild!)
24 4. When you are happy with a change make it generally available for
25 testing in gerrit and await feedback.
27 5. Make your patch available through coreboot's gerrit code review
28 system, and add the relevant maintainer from this list as a code
29 reviewer. Be prepared to get your changes sent back with seemingly
30 silly requests about formatting and variable names. These aren't
31 as silly as they seem. One job the maintainers do is to keep
32 things looking the same. Sometimes this means that the clever
33 hack in your mainboard or chipset to get around a problem actually
34 needs to become a generalized coreboot feature ready for next time.
36 PLEASE check your patch with the automated style checker
37 (util/lint/checkpatch.pl) to catch trival style violations.
38 See http://coreboot.org/Coding_Style for guidance here.
40 PLEASE add the maintainers that are generated by
41 util/scripts/get_maintainer.pl as reviewers. The results returned
42 by the script will be best if you have git installed and are
43 making your changes in a branch derived from coreboot.org's latest
46 PLEASE try to include any credit lines you want added with the
47 patch. It avoids people being missed off by mistake and makes
48 it easier to know who wants adding and who doesn't.
50 PLEASE document known bugs. If it doesn't work for everything
51 or does something very odd once a month document it.
53 PLEASE remember that submissions must be made under the terms
54 of the OSDL certificate of contribution and should include a
55 Signed-off-by: line. The current version of this "Developer's
56 Certificate of Origin" (DCO) is listed at
57 http://coreboot.org/Development_Guidelines#Sign-off_Procedure.
59 6. Make sure you have the right to send any changes you make. If you
60 do changes at work you may find your employer owns the patch
65 Descriptions of section entries:
67 M: Maintainer: FullName <address@domain>
68 R: Designated reviewer: FullName <address@domain>
69 These reviewers should be CCed on patches.
70 L: Mailing list that is relevant to this area
71 W: Web-page with status/info
72 Q: Patchwork web based patch tracking system site
73 T: SCM tree type and location.
74 Type is one of: git, hg, quilt, stgit, topgit
75 S: Status, one of the following:
76 Supported: Someone is actually paid to look after this.
77 Maintained: Someone actually looks after it.
78 Odd Fixes: It has a maintainer but they don't have time to do
79 much other than throw the odd patch in. See below..
80 Orphan: No current maintainer [but maybe you could take the
81 role as you write your new code].
82 Obsolete: Old code. Something tagged obsolete generally means
83 it has been replaced by a better system and you
85 F: Files and directories with wildcard patterns.
86 A trailing slash includes all files and subdirectory files.
87 F: drivers/net/ all files in and below drivers/net
88 F: drivers/net/* all files in drivers/net, but not below
89 F: */net/* all files in "any top level directory"/net
90 One pattern per line. Multiple F: lines acceptable.
91 N: Files and directories with regex patterns.
92 N: [^a-z]tegra all files whose path contains the word tegra
93 One pattern per line. Multiple N: lines acceptable.
94 scripts/get_maintainer.pl has different behavior for files that
95 match F: pattern and matches of N: patterns. By default,
96 get_maintainer will not look at git log history when an F: pattern
97 match occurs. When an N: match occurs, git log history is used
98 to also notify the people that have git commit signatures.
99 X: Files and directories that are NOT maintained, same rules as F:
100 Files exclusions are tested before file matches.
101 Can be useful for excluding a specific subdirectory, for instance:
104 matches all files in and below net excluding net/ipv6/
105 K: Keyword perl extended regex pattern to match content in a
106 patch or file. For instance:
108 matches patches or files that contain "of_get_profile"
109 K: \b(printk|pr_(info|err))\b
110 matches patches or files that contain one or more of the words
111 printk, pr_info or pr_err
112 One regex pattern per line. Multiple K: lines acceptable.
114 Note: For the hard of thinking, this list is meant to remain in alphabetical
115 order. If you could add yourselves to it in alphabetical order that would be
118 Maintainers List (try to look for most precise areas first)
120 -----------------------------------
123 M: Ronald Minnich <rminnich@gmail.com>
124 M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
129 F: src/mainboard/emulation/*-riscv/
130 F: src/mainboard/lowrisc
133 M: Ronald Minnich <rminnich@gmail.com>
134 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
137 F: src/cpu/qemu-power8/
138 F: src/mainboard/emulation/qemu-power8/
141 M: Alexander Couzens <lynxis@fe80.eu>
146 M: Alexander Couzens <lynxis@fe80.eu>
147 M: Patrick Rudolph <siro@das-labor.org>
149 F: src/mainboard/lenovo/
151 INTEL PINEVIEW CHIPSET
152 M: Damien Zammit <damien@zamaudio.com>
154 F: src/northbridge/intel/pineview/
156 INTEL D510MO MAINBOARD
157 M: Damien Zammit <damien@zamaudio.com>
159 F: src/mainboard/intel/d510mo
162 M: Damien Zammit <damien@zamaudio.com>
164 F: src/northbridge/intel/x4x/
166 GIGABYTE GA-G41M-ES2L MAINBOARD
167 M: Damien Zammit <damien@zamaudio.com>
169 F: src/mainboard/gigabyte/ga-g41m-es2l
171 GOOGLE PANTHER MAINBOARD
172 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
174 F: src/mainboard/google/panther/
176 INTEL MINNOWBOARD MAX MAINBOARD
177 M: Huang Jin <huang.jin@intel.com>
178 M: York Yang <york.yang@intel.com>
179 M: Martin Roth <gaumless@gmail.com>
181 F: src/mainboard/intel/minnowmax/
183 INTEL FSP BAYTRAIL CHIP & CRBs
184 M: Huang Jin <huang.jin@intel.com>
185 M: York Yang <york.yang@intel.com>
186 M: Martin Roth <gaumless@gmail.com>
188 F: src/soc/intel/fsp_baytrail/
189 F: src/vendorcode/intel/fsp1_0/baytrail/
190 F: src/mainboard/intel/bakersport_fsp/
191 F: src/mainboard/intel/bayleybay_fsp/
193 INTEL FSP BROADWELL-DE SOC & CRB
194 M: York Yang <york.yang@intel.com>
196 F: src/soc/intel/fsp_broadwell_de/
197 F: src/vendorcode/intel/fsp1_0/broadwell_de/
198 F: src/mainboard/intel/camelbackmountain_fsp/
200 INTEL FSP IVYBRIDGE/PANTHERPOINT/CAVECREEK & CRBs
201 M: York Yang <york.yang@intel.com>
203 F: src/cpu/intel/fsp_model_206ax/
204 F: src/northbridge/intel/fsp_sandybridge/
205 F: src/southbridge/intel/fsp_bd82x6x/
206 F: src/southbridge/intel/fsp_i89xx/
207 F: src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x
208 F: src/vendorcode/intel/fsp1_0/ivybridge_i89xx
209 F: src/mainboard/intel/cougar_canyon2/
210 F: src/mainboard/intel/stargo2/
212 FSP 1.0 RANGELEY & CRB
213 M: David Guckian <david.guckian@intel.com>
214 M: Fei Wang <fei.z.wang@intel.com>
216 F: src/cpu/intel/fsp_model_406dx/
217 F: src/northbridge/intel/fsp_rangeley/
218 F: src/southbridge/intel/fsp_rangeley/
219 F: src/vendorcode/intel/fsp1_0/rangeley/
220 F: src/mainboard/intel/mohonpeak/
222 INTEL LITTLE PLAINS MAINBOARD
223 M: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
225 F: src/mainboard/intel/littleplains/
228 M: Huang Jin <huang.jin@intel.com>
229 M: York Yang <york.yang@intel.com>
230 M: Martin Roth <gaumless@gmail.com>
232 F: src/drivers/intel/fsp1_0/
235 M: Lee Leahy <leroy.p.leahy@intel.com>
236 M: Andrey Petrov <andrey.petrov@intel.com>
237 M: Huang Jin <huang.jin@intel.com>
238 M: York Yang <york.yang@intel.com>
240 F: src/drivers/intel/fsp1_1/
243 M: Andrey Petrov <andrey.petrov@intel.com>
245 F: src/drivers/intel/fsp2_0/
247 INTEL STRAGO MAINBOARD
248 M: Hannah Williams <hannah.williams@intel.com>
250 F: /src/mainboard/intel/strago/
253 M: Hannah Williams <hannah.williams@intel.com>
255 F: /src/soc/intel/braswell
256 F: /src/vendorcode/intel/fsp/fsp1_1/braswell
259 M: Andrey Petrov <andrey.petrov@intel.com>
261 F: src/soc/intel/apollolake/
263 ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
264 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
266 F: src/mainboard/asus/kfsn4-dre/
267 F: src/mainboard/asus/kfsn4-dre_k8/
269 ASUS KCMA-D8 MAINBOARD
270 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
272 F: src/mainboard/asus/kcma-d8/
274 ASUS KGPE-D16 MAINBOARD
275 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
277 F: src/mainboard/asus/kgpe-d16/
279 AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
280 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
282 F: src/cpu/amd/family_10h-family_15h/
283 F: src/northbridge/amd/amdfam10/
284 F: src/northbridge/amd/amdmct/
285 F: src/northbridge/amd/amdht/
287 AMD SB700 (NON-CIMX) SOUTHBRIDGE
288 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
290 F: src/southbridge/amd/sb700/
292 AMD SR5650 SOUTHBRIDGE
293 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
295 F: src/southbridge/amd/sr5650/
297 ASPEED AST2050 DRIVER & COMMON CODE
298 M: Timothy Pearson <tpearson@raptorengineeringinc.com>
300 F: src/drivers/aspeed/common/
301 F: src/drivers/aspeed/ast2050/
305 F: src/drivers/ati/mach64/
308 M: Patrick Georgi <patrick@georgi-clan.de>
309 M: Martin Roth <gaumless@gmail.com>
315 F: src/arch/x86/acpi/
321 F: src/cpu/allwinner/
331 F: util/arm_boot_tools/
349 F: src/include/cpu/x86/
352 M: Patrick Rudolph <siro@das-labor.org>
354 F: src/vendorcode/intel/
356 F: src/northbridge/intel/
357 F: src/southbridge/intel/
359 F: src/drivers/intel/
360 F: src/include/cpu/intel/
363 F: src/vendorcode/amd/
365 F: src/northbridge/amd/
366 F: src/southbridge/amd/
367 F: src/include/cpu/amd/
371 F: src/northbridge/via/
372 F: src/southbridge/via/
375 M: Patrick Georgi <patrick@georgi-clan.de>
376 M: Martin Roth <gaumless@gmail.com>
381 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
385 M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
389 M: Nicola Corna <nicola@corna.info>
390 W: https://github.com/corna/me_cleaner
395 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
400 M: Patrick Georgi <patrick@georgi-clan.de>
401 M: Martin Roth <gaumless@gmail.com>
405 F: src/include/kconfig.h
412 M: Martin Roth <gaumless@gmail.com>
414 F: util/board_status/
421 F: src/vendorcode/google/chromeos/
423 F: src/include/tpm_lite/
427 F: src/include/device/
428 F: src/include/cpu/cpu.h
430 OPTION ROM EXECUTION & X86EMU
434 F: src/include/cbfs.h
435 F: src/include/cbfs_serialized.h
439 F: src/include/cbmem.h
440 F: src/include/cbmem_id.h
445 F: src/include/console/
451 F: payloads/nvramcui/
454 F: payloads/libpayload/
460 F: payloads/coreinfo/
462 EXTERNAL PAYLOADS INTEGRATION
463 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
464 M: Martin Roth <gaumless@gmail.com>
468 M: Aaron Durbin <adurbin@chromium.org>
469 F: src/vendorcode/google/chromeos/vboot2/
472 M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
473 F: src/drivers/*/tpm/
474 F: src/security/tpm12/
475 F: src/security/tpm20/
476 F: util/tss-generator/
479 M: Martin Roth <gaumless@gmail.com>
484 M: Martin Roth <gaumless@gmail.com>
489 M: Martin Roth <gaumless@gmail.com>
494 MISSING: TIMERS / DELAYS
508 MISSING: DMP / QEMU-X86
515 M: Stefan Reinauer <stefan.reinauer@coreboot.org>
516 T: git http://review.coreboot.org/coreboot
517 S: Buried alive in mainboards