src/mainboard/lippert/frontrunner-af/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include <PlatformMemoryConfiguration.h>
  18
  19 #include <northbridge/amd/agesa/state_machine.h>
  20
  21 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  22         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  23         {
  24                 0,
  25                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  26                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
  27         },
  28         // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  29         {
  30                 0,
  31                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  32                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
  33         },
  34         // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  35         {
  36                 0,
  37                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
  38                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
  39         },
  40         // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  41         {
  42                 0,
  43                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
  44                 PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
  45         },
  46         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  47         {
  48                 DESCRIPTOR_TERMINATE_LIST,
  49                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
  50                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0)
  51         }
  52 };
  53
  54 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  55         // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  56         {
  57                 0,
  58                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  59                 //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
  60                 {ConnectorTypeTravisDpToLvds, Aux1, Hdp1}
  61         },
  62         // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  63         {
  64                 DESCRIPTOR_TERMINATE_LIST,
  65                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  66                 //PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
  67                 {ConnectorTypeDP, Aux2, Hdp2}
  68         }
  69 };
  70
  71 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  72         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  73         .SocketId     = 0,
  74         .PciePortList = PortList,
  75         .DdiLinkList  = DdiList,
  76 };
  77
  78 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  79 {
  80         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  81         InitEarly->GnbConfig.PsppPolicy         = 0;
  82 }
  83
  84 /*----------------------------------------------------------------------------------------
  85  *                                              CUSTOMER OVERIDES MEMORY TABLE
  86  *----------------------------------------------------------------------------------------
  87  */
  88
  89 /*
  90  *      Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  91  *      (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
  92  *      is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  93  *      use its default conservative settings.
  94  */
  95 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
  96         HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
  97         NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
  98         NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
  99         PSO_END
 100 };
 101
 102 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 103 {
 104         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 105 }