src/mainboard/jetway/nf81-t56n-lf/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18
  19 #include <arch/io.h>
  20 #include <console/console.h>
  21 #include <device/device.h>
  22
  23 #include <southbridge/amd/common/amd_pci_util.h>
  24 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
  25 #include <southbridge/amd/cimx/sb800/pci_devs.h>
  26 #include <southbridge/amd/cimx/cimx_util.h>
  27 #include <northbridge/amd/agesa/family14/pci_devs.h>
  28
  29 /***********************************************************
  30  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  31  * This table is responsible for physically routing the PIC and
  32  * IOAPIC IRQs to the different PCI devices on the system.  It
  33  * is read and written via registers 0xC00/0xC01 as an
  34  * Index/Data pair.  These values are chipset and mainboard
  35  * dependent and should be updated accordingly.
  36  *
  37  * These values are used by the PCI configuration space,
  38  * MP Tables.  TODO: Make ACPI use these values too.
  39  *
  40  * The Persimmon PCI INTA/B/C/D pins are connected to
  41  * FCH pins INTE/F/G/H on the schematic so these need
  42  * to be routed as well.
  43  */
  44 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  45         /* INTA# - INTH# */
  46         [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  47         /* Misc-nil,0,1,2, INT from Serial irq */
  48         [0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  49         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
  50         [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
  51         /* IMC INT0 - 5 */
  52         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  53         /* USB Devs 18/19/20/22 INTA-C */
  54         [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
  55         /* IDE, SATA */
  56         [0x40] = 0x0B,0x0B,
  57         /* GPPInt0 - 3 */
  58         [0x50] = 0x0A,0x0B,0x0A,0x0B
  59 };
  60
  61 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  62         /* INTA# - INTH# */
  63         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
  64         /* Misc-nil,0,1,2, INT from Serial irq */
  65         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  66         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
  67         [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
  68         /* IMC INT0 - 5 */
  69         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  70         /* USB Devs 18/19/22/20 INTA-C */
  71         [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
  72         /* IDE, SATA */
  73         [0x40] = 0x11,0x13,
  74         /* GPPInt0 - 3 */
  75         [0x50] = 0x10,0x11,0x12,0x13
  76 };
  77
  78 /*
  79  * This table defines the index into the picr/intr_data
  80  * tables for each device.  Any enabled device and slot
  81  * that uses hardware interrupts should have an entry
  82  * in this table to define its index into the FCH
  83  * PCI_INTR register 0xC00/0xC01.  This index will define
  84  * the interrupt that it should use.  Putting PIRQ_A into
  85  * the PIN A index for a device will tell that device to
  86  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  87  */
  88 /*
  89  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
  90  * but because PCI INT_PIN swizzling isnt implemented to match
  91  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  92  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  93  * off-chip devices should get mapped to PIRQH/E/F/G.
  94  */
  95 static const struct pirq_struct mainboard_pirq_data[] = {
  96         /* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
  97         {GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
  98         {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
  99         {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
 100         {SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
 101         {OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
 102         {EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
 103         {OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
 104         {EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
 105         {SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
 106         {IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
 107         {HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
 108         {SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
 109         {OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
 110         {OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
 111         {EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
 112 };
 113
 114 /* PIRQ Setup */
 115 static void pirq_setup(void)
 116 {
 117         pirq_data_ptr = mainboard_pirq_data;
 118         pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
 119         intr_data_ptr = mainboard_intr_data;
 120         picr_data_ptr = mainboard_picr_data;
 121 }
 122
 123 /**********************************************
 124  * Enable the dedicated functions of the board.
 125  **********************************************/
 126 static void mainboard_enable(device_t dev)
 127 {
 128         printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 129
 130         /* enable GPP CLK0 thru CLK3 (interleaved) */
 131         /* disable GPP CLK4 thru SLT_GFX_CLK */
 132         u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
 133         write8(misc_mem_clk_cntrl + 0, 0xFF);
 134         write8(misc_mem_clk_cntrl + 1, 0xFF);
 135         write8(misc_mem_clk_cntrl + 2, 0x00);
 136         write8(misc_mem_clk_cntrl + 3, 0x00);
 137         write8(misc_mem_clk_cntrl + 4, 0x00);
 138
 139         /*
 140          * Initialize ASF registers to an arbitrary address because someone
 141          * long ago set things up this way inside the SPD read code. The
 142          * SPD read code has been made generic and moved out of the board
 143          * directory, so the ASF init is being done here.
 144          */
 145         pm_iowrite(0x29, 0x80);
 146         pm_iowrite(0x28, 0x61);
 147
 148         /* Initialize the PIRQ data structures for consumption */
 149         pirq_setup();
 150 }
 151
 152 struct chip_operations mainboard_ops = {
 153         .enable_dev = mainboard_enable,
 154 };