src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17
  18 #include <AGESA.h>
  19 #include <northbridge/amd/agesa/state_machine.h>
  20 #include <PlatformMemoryConfiguration.h>
  21
  22 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  23         /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
  24         {
  25                 0,
  26                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  27                 PCIE_PORT_DATA_INITIALIZER(PortEnabled,
  28                                                 ChannelTypeExt6db,
  29                                                 4,
  30                                                 HotplugDisabled,
  31                                                 PcieGen2,
  32                                                 PcieGen2,
  33                                                 AspmL0sL1,
  34                                                 46)
  35         },
  36         /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
  37         {
  38                 0,
  39                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  40                 PCIE_PORT_DATA_INITIALIZER(PortEnabled,
  41                                                 ChannelTypeExt6db,
  42                                                 5,
  43                                                 HotplugDisabled,
  44                                                 PcieGen2,
  45                                                 PcieGen2,
  46                                                 AspmL0sL1,
  47                                                 46)
  48         },
  49         /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
  50         {
  51                 0,
  52                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
  53                 PCIE_PORT_DATA_INITIALIZER(PortEnabled,
  54                                                 ChannelTypeExt6db,
  55                                                 6,
  56                                                 HotplugDisabled,
  57                                                 PcieGen2,
  58                                                 PcieGen2,
  59                                                 AspmL0sL1,
  60                                                 46)
  61         },
  62         /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
  63         {
  64                 0,
  65                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
  66                 PCIE_PORT_DATA_INITIALIZER(PortDisabled,
  67                                                 ChannelTypeExt6db,
  68                                                 7,
  69                                                 HotplugDisabled,
  70                                                 PcieGen2,
  71                                                 PcieGen2,
  72                                                 AspmL0sL1,
  73                                                 0)
  74         },
  75         /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
  76         {
  77                 DESCRIPTOR_TERMINATE_LIST,
  78                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
  79                 PCIE_PORT_DATA_INITIALIZER(PortEnabled,
  80                                                 ChannelTypeExt6db,
  81                                                 8,
  82                                                 HotplugDisabled,
  83                                                 PcieGen2,
  84                                                 PcieGen2,
  85                                                 AspmL0sL1,
  86                                                 0)
  87         }
  88 };
  89
  90 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  91         /* (DDI interface Lanes 8:11, DdA, ...) */
  92         {
  93                 0,
  94                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  95                 /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
  96                 {ConnectorTypeLvds, Aux1, Hdp1}
  97         },
  98         /* (DDI interface Lanes 12:15, DdB, ...) */
  99         {
 100                 DESCRIPTOR_TERMINATE_LIST,
 101                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
 102                 /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
 103                 {ConnectorTypeDP, Aux2, Hdp2}
 104         }
 105 };
 106
 107 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 108         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 109         .SocketId     = 0,
 110         .PciePortList = PortList,
 111         .DdiLinkList  = DdiList,
 112 };
 113
 114 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 115 {
 116         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 117         InitEarly->GnbConfig.PsppPolicy         = 0;
 118 }
 119
 120 /**
 121  * @brief Customer Overides Memory Table
 122  *
 123  * Platform Specific Overriding Table allows IBV/OEM to pass in platform
 124  * information to AGESA
 125  * (e.g. MemClk routing, the number of DIMM slots per channel,...).
 126  * If PlatformSpecificTable is populated, AGESA will base its settings on the
 127  * data from the table. Otherwise, it will use its default conservative settings.
 128  */
 129 static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 130         NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
 131         NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
 132         PSO_END
 133 };
 134
 135 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 136 {
 137         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 138 }