src/mainboard/google/deltaur/variants/baseboard/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * SPDX-License-Identifier: GPL-2.0-or-later
   5  */
   6
   7 #include <arch/acpi.h>
   8 #include <baseboard/variants.h>
   9 #include <baseboard/gpio.h>
  10 #include <soc/gpio.h>
  11 #include <variant/gpio.h>
  12
  13 static const struct pad_config gpio_table[] = {
  14         /* A0 thru A6 are ESPI, configured elsewhere */
  15         /* A0  : ESPI_IO0 ==> ESPI_IO_0 */
  16         /* A1  : ESPI_IO1 ==> ESPI_IO_1 */
  17         /* A2  : ESPI_IO2 ==> ESPI_IO_2 */
  18         /* A3  : ESPI_IO3 ==> ESPI_IO_3 */
  19         /* A4  : ESPI_CS# ==> ESPI_CS_L */
  20         /* A5  : ESPI_CLK ==> ESPI_CLK */
  21         /* A6  : ESPI_RESET# ==> NC(TP764) */
  22         /* A7  : GPP_A7 ==> CNVI_EN# */
  23         PAD_CFG_GPI(GPP_A7, NONE, DEEP),
  24         /* A8  : GPP_A8 ==> CNV_RF_RESET# */
  25         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
  26         /* A9  : GPP_A9 ==> CLKREQ_CNV#_1P8 */
  27         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2),
  28         /* A10 : GPP_A10 ==> TOUCH_SCREEN_RST# */
  29         PAD_CFG_GPO(GPP_A10, 0, DEEP),
  30         /* A11 : GPP_A11 ==> NC */
  31         PAD_NC(GPP_A11, NONE),
  32         /* A12 : GPP_A12 ==> M2280_PCIE_SATA# */
  33         PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
  34         /* A13 : GPP_A13 ==> PCH_BT_RADIO_DIS# */
  35         PAD_CFG_GPO(GPP_A13, 0, DEEP),
  36         /* A14 : GPP_A14 ==> USB_OC1# */
  37         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  38         /* A15 : GPP_A15 ==> USB_OC2# */
  39         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  40         /* A16 : GPP_A16 ==> USB_OC3# */
  41         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  42         /* A17 : GPP_A17 ==> NC */
  43         PAD_NC(GPP_A17, NONE),
  44         /* A18 : GPP_A18 ==> HDMI_HPD */
  45         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  46         /* A19 : GPP_A19 ==> NC */
  47         PAD_NC(GPP_A19, NONE),
  48         /* A20 : GPP_A20 ==> NC */
  49         PAD_NC(GPP_A20, NONE),
  50         /* A21 : GPP_A21 ==> 3.3V_CAM_EN# */
  51         PAD_CFG_GPO(GPP_A21, 0, PLTRST),
  52         /* A22 : GPP_A22 ==> KB_DET# */
  53         PAD_CFG_GPI(GPP_A22, NONE, PLTRST),
  54         /* A23 : GPP_A23 ==> RECOVERY# */
  55         PAD_CFG_GPI(GPP_A23, NONE, DEEP),
  56
  57         /* B0  : GPP_B0 ==> CORE_VID0 */
  58         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  59         /* B1  : GPP_B1 ==> CORE_VID1 */
  60         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  61         /* B2  : GPP_B2 ==> VRALERT_L */
  62         PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
  63         /* B3  : GPP_B3 ==> TOUCH_SCREEN_PD# */
  64         PAD_CFG_GPO(GPP_B3, 0, PLTRST),
  65         /* B4  : GPP_B4 ==> TOUCH_SCREEN_DET# */
  66         PAD_CFG_GPI(GPP_B4, NONE, DEEP),
  67         /* B5  : GPP_B5 ==> ISH_I2C0_SDA */
  68         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  69         /* B6  : GPP_B6 ==> ISH_I2C0_SCL */
  70         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  71         /* B7  : GPP_B7 ==> NC */
  72         PAD_NC(GPP_B7, NONE),
  73         /* B8  : GPP_B8 ==> NC */
  74         PAD_NC(GPP_B8, NONE),
  75         /* B9  : GPP_B9 ==> NC */
  76         PAD_NC(GPP_B9, NONE),
  77         /* B10 : GPP_B10 ===> NC */
  78         PAD_NC(GPP_B10, NONE),
  79         /* B11 : GPP_B11 ==> TBT_I2C_INT# */
  80         PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT),
  81         /* B12 : GPP_B12 ==> SIO_SLP_S0# */
  82         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  83         /* B13 : PLTRST# ==> PCH_PLTRST# */
  84         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  85         /* B14 : GPP_B14 ==> SPKR (PIN STRAP, Top Swap Override) */
  86         PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
  87         /* B15 : GPP_B15 ==> SPK_DET0# */
  88         PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
  89         /* B16 : GPP_B16 ==> ONE_DIMM# */
  90         PAD_CFG_GPI(GPP_B16, NONE, PLTRST),
  91         /* B17 : GPP_B17 ==> HOST_SD_WP# */
  92         PAD_CFG_GPO(GPP_B17, 0, PLTRST),
  93         /* B18 : GPP_B18 ==> NRB_BIT (PIN STRAP, No Reboot) */
  94         PAD_NC(GPP_B18, NONE),
  95         /* B19 : GPP_B19 ==> D3_RST# */
  96         PAD_CFG_GPO(GPP_B19, 0, DEEP),
  97         /* B20 : GPP_B20 ==> LCD_CBL_DET# */
  98         PAD_CFG_GPI(GPP_B20, NONE, PLTRST),
  99         /* B21 : GPP_B21 ==> PCH_TOUCH_SCREEN_EN */
 100         PAD_CFG_GPO(GPP_B21, 0, DEEP),
 101         /* B22 : GPP_B22 ==> NC */
 102         PAD_NC(GPP_B22, NONE),
 103         /* B23 : GPP_B23 ==> NC (PIN STRAP, CPUNSSC frequency) */
 104         PAD_NC(GPP_B23, NONE),
 105
 106         /* C0  : GPP_C0 ==> MEM_SMBCLK */
 107         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 108         /* C1  : GPP_C1 ==> MEM_SMBDATA */
 109         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 110         /* C2  : GPP_C2 ==> NC (PIN STRAP, TLS Confidentiality) */
 111         PAD_NC(GPP_C2, NONE),
 112         /* C3  : GPP_C3 ==> SML0_SMBCLK */
 113         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 114         /* C4  : GPP_C4 ==> SML0_SMBDATA */
 115         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
 116         /* C5  : GPP_C5 ==> NC (PIN STRAP, Boot Strap 0) */
 117         PAD_NC(GPP_C5, NONE),
 118         /* C6  : GPP_C6 ==> SML1_SMBCLK */
 119         PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 120         /* C7  : GPP_C7 ==> SML1_SMBDATA */
 121         PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
 122         /* C8  : GPP_C8 ==> WWAN_FULL_POWER_EN */
 123         PAD_CFG_GPO(GPP_C8, 1, DEEP),
 124         /* C9  : GPP_C9 ==> SBIOS_TX */
 125         PAD_CFG_GPO(GPP_C9, 0, PLTRST),
 126         /* C10 : GPP_C10 ==> NC */
 127         PAD_NC(GPP_C10, NONE),
 128         /* C11 : GPP_C11 ==> NC */
 129         PAD_NC(GPP_C11, NONE),
 130         /* C12 : GPP_C12 ==> NC */
 131         PAD_NC(GPP_C12, NONE),
 132         /* C13 : GPP_C13 ==> PCH_SSD_PWR_EN */
 133         PAD_CFG_GPO(GPP_C13, 1, DEEP),
 134         /* C14 : GPP_C14 ==> NC */
 135         PAD_NC(GPP_C14, NONE),
 136         /* C15 : GPP_C15 ==> NC */
 137         PAD_NC(GPP_C15, NONE),
 138         /* C16 : GPP_C16 ==> I2C0_SDA_TS */
 139         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 140         /* C17 : GPP_C17 ==> I2C0_SCL_TS */
 141         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 142         /* C18 : GPP_C18 ==> I2C1_SDA_TP */
 143         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 144         /* C19 : GPP_C19 ==> I2C1_SCL_TP */
 145         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 146         /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
 147         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 148         /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
 149         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 150         /* C22 : GPP_C22 ==> H1_FLASH_WP */
 151         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 152         /* C23 : GPP_C23 ==> H1_PCH_INT# */
 153         PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
 154
 155         /* D0  : GPP_D0 ==> ISH_ACC1_INT */
 156         PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
 157         /* D1  : GPP_D1 ==> ISH_ACC2_INT */
 158         PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 159         /* D2  : GPP_D2 ==> ISH_TABLE_MODE# */
 160         PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
 161         /* D3  : GPP_D3 ==> ISH_ALS_INT# */
 162         PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
 163         /* D4  : GPP_D4 ==> RT_FORCE_PWR */
 164         PAD_CFG_GPO(GPP_D4, 0, PLTRST),
 165         /* D5  : GPP_D5 ==> CLKREQ_PCIE#0 */
 166         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 167         /* D6  : GPP_D6 ==> CLKREQ_PCIE#1 */
 168         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 169         /* D7  : GPP_D7 ==> CLKREQ_PCIE#2 */
 170         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 171         /* D8  : GPP_D8 ==> CLKREQ_PCIE#3 */
 172         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 173         /* D9  : GPP_D9 ==> TBT_2_LSX_TX */
 174         PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
 175         /* D10 : GPP_D10 ==> TBT_2_LSX_RX */
 176         PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
 177         /* D11 : GPP_D11 ==> TBT_3_LSX_TX */
 178         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
 179         /* D12 : GPP_D12 ==> TBT_3_LSX_RX */
 180         PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF4),
 181         /* D13 : GPP_D13 ==> SML0B_SMLDATA */
 182         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
 183         /* D14 : GPP_D14 ==> SML0B_SMLCLK */
 184         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2),
 185         /* D15 : GPP_D15 ==> NC */
 186         PAD_NC(GPP_D15, NONE),
 187         /* D16 : GPP_D16 ==> SML0BALERT# */
 188         PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
 189         /* D17 : GPP_D17 ==> ISH_NB_MODE# */
 190         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 191         /* D18 : GPP_D18 ==> ISH_LID_CL#_NB */
 192         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 193         /* D19 : GPP_D19 ==> NC */
 194         PAD_NC(GPP_D19, NONE),
 195
 196         /* E0  : GPP_E0 ==> NC */
 197         PAD_NC(GPP_E0, NONE),
 198         /* E1  : GPP_E1 ==> TOUCH_SCREEN_INT# */
 199         PAD_CFG_GPI_APIC(GPP_E1, NONE, PLTRST, LEVEL, INVERT),
 200         /* E2  : GPP_E2 ==> MEDIACARD_IRQ# */
 201         PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT),
 202         /* E3  : GPP_E3 ==> MEM_INTERLEAVED */
 203         PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
 204         /* E4  : GPP_E4 ==> NC */
 205         PAD_NC(GPP_E4, NONE),
 206         /* E5  : GPP_E5 ==> M2280_DEVSLP */
 207         PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
 208         /* E6  : GPP_E6 ==> (PIN STRAP, Reserved) */
 209         PAD_NC(GPP_E6, NONE),
 210         /* E7  : CPU_GP1 ==> PCH_TOUCHPAD_INTR# */
 211         PAD_CFG_GPI_IRQ_WAKE(GPP_E7, NONE, PLTRST, LEVEL, INVERT),
 212         /* E8  : GPP_E8 ==> SECURE_BIO */
 213         PAD_CFG_GPO(GPP_E8, 0, PLTRST),
 214         /* E9  : GPP_E9 ==> OC0# */
 215         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 216         /* E10 : GPP_E10 ==> HDMI_PD# */
 217         PAD_CFG_GPO(GPP_E10, 1, DEEP),
 218         /* E11 : GPP_E11 ==> VPRO_DET# */
 219         PAD_CFG_GPI(GPP_E11, NONE, PLTRST),
 220         /* E12 : GPP_E12 ==> RTC_DET# */
 221         PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
 222         /* E13 : GPP_E13 ==> TBT_DET# */
 223         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 224         /* E14 : GPP_E14 ==> EPD_HPD */
 225         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 226         /* E15 : GPP_E15 ==> ISH_LID_CL#_TAB */
 227         PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
 228         /* E16 : GPP_E16 ==> NC */
 229         PAD_NC(GPP_E16, NONE),
 230         /* E17 : GPP_E17 ==> NC */
 231         PAD_NC(GPP_E17, NONE),
 232         /* E18 : GPP_E18 ==> TBT_LSX0_TXD */
 233         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
 234         /* E19 : GPP_E19 ==> TBT_LSX0_RXD */
 235         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
 236         /* E20 : GPP_E20 ==> TBT_LSX1_TXD */
 237         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
 238         /* E21 : GPP_E21 ==> TBT_LSX1_RXD */
 239         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 240         /* E22 : GPP_E22 ==> NC */
 241         PAD_NC(GPP_E22, NONE),
 242         /* E23 : GPP_E23 ==> NC */
 243         PAD_NC(GPP_E23, NONE),
 244
 245         /* F0  : GPP_F0 ==> BRI_DT_1P8 */
 246         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 247         /* F1  : GPP_F1 ==> CNV_BRI_RSP_1P8 */
 248         PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
 249         /* F2  : GPP_F2 ==> CNV_RGI_DT_1P8 */
 250         PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
 251         /* F3  : GPP_F3 ==> CNV_RGI_RSP_1P8 */
 252         PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
 253         /* F4  : GPP_F4 ==> NC */
 254         PAD_NC(GPP_F4, NONE),
 255         /* F5  : GPP_F5 ==> NC */
 256         PAD_NC(GPP_F5, NONE),
 257         /* F6  : GPP_F6 ==> NC */
 258         PAD_NC(GPP_F6, NONE),
 259         /* F7  : GPP_F7 ==> NC (PIN STRAP, Reserved) */
 260         PAD_NC(GPP_F7, NONE),
 261         /* F8  : GPP_F8 ==> NC */
 262         PAD_NC(GPP_F8, NONE),
 263         /* F9  : GPP_F9 ==> NC */
 264         PAD_NC(GPP_F9, NONE),
 265         /* F10 : GPP_F10 ==> NC (PIN STRAP, Reserved) */
 266         PAD_NC(GPP_F10, NONE),
 267         /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
 268         PAD_CFG_GPI(GPP_F11, NONE, DEEP),
 269         /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
 270         PAD_CFG_GPI(GPP_F12, NONE, DEEP),
 271         /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
 272         PAD_CFG_GPI(GPP_F13, NONE, DEEP),
 273         /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
 274         PAD_CFG_GPI(GPP_F14, NONE, DEEP),
 275         /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
 276         PAD_CFG_GPI(GPP_F15, NONE, DEEP),
 277         /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
 278         PAD_CFG_GPO(GPP_F16, 1, DEEP),
 279         /* F17 : GPP_F17 ==> WWAN_GPIO_PERST# */
 280         PAD_CFG_GPO(GPP_F17, 0, DEEP),
 281         /* F18 : GPP_F18 ==> WWAN_GPIO_WAKE# */
 282         PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
 283         /* F19 : GPP_F19 ==> CAM_MIC_CBL_DET# */
 284         PAD_CFG_GPI(GPP_F19, NONE, PLTRST),
 285         /* F20 : GPP_F20 ==> NC */
 286         PAD_NC(GPP_F20, NONE),
 287         /* F21 : GPP_F21 ==> NC */
 288         PAD_NC(GPP_F21, NONE),
 289         /* F22 : VNN_CTRL */
 290         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 291         /* F23 : V1P05_CTRL */
 292         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 293
 294         /* H0  : GPPH0_BOOT_STRAP1 */
 295         PAD_NC(GPP_H0, NONE),
 296         /* H1  : GPPH1_BOOT_STRAP2 */
 297         PAD_NC(GPP_H1, NONE),
 298         /* H2  : GPPH2_BOOT_STRAP3 */
 299         PAD_NC(GPP_H2, NONE),
 300         /* H3  : GPP_H3 ==> NC */
 301         PAD_NC(GPP_H3, NONE),
 302         /* H4  : GPP_H4 ==> DDR_CHA_EN_1P8 */
 303         PAD_CFG_GPI(GPP_H4, NONE, DEEP),
 304         /* H5  : GPP_H5 ==> DDR_CHB_EN_1P8 */
 305         PAD_CFG_GPI(GPP_H5, NONE, DEEP),
 306         /* H6  : GPP_H6 ==> SPK_DET1 */
 307         PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
 308         /* H7  : GPP_H7 ==> NC */
 309         PAD_NC(GPP_H7, NONE),
 310         /* H8  : GPP_H8 ==> I2C_SDA_PCH_H1 */
 311         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 312         /* H9  : GPP_H9 ==> I2C_SCL_PCH_H1 */
 313         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 314         /* H10 : GPP_H10 ==> CLKREQ_PCIE#4 */
 315         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 316         /* H11 : GPP_H11 ==> CLKREQ_PCIE#5 */
 317         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
 318         /* H12 : GPP_H12 ==> NC */
 319         PAD_NC(GPP_H12, NONE),
 320         /* H13 : GPP_H13 ==> NC */
 321         PAD_NC(GPP_H13, NONE),
 322         /* H14 : GPP_H14 ==> NC */
 323         PAD_NC(GPP_H14, NONE),
 324         /* H15 : GPP_H15 ==> NC */
 325         PAD_NC(GPP_H15, NONE),
 326         /* H16 : GPP_H16 ==> CPU_DPB_CTRL_CLK */
 327         PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
 328         /* H17 : GPP_H17 ==> CPU_DPB_CTRL_DATA */
 329         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
 330         /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE# */
 331         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 332         /* H19 : GPP_H19 ==> NC */
 333         PAD_NC(GPP_H19, NONE),
 334         /* H20 : GPP_H20 ==> NC */
 335         PAD_NC(GPP_H20, NONE),
 336         /* H21 : GPP_H21 ==> NC */
 337         PAD_NC(GPP_H21, NONE),
 338         /* H22 : GPP_H22 ==> NC */
 339         PAD_NC(GPP_H22, NONE),
 340         /* H23 : GPP_H23 ==> NC */
 341         PAD_NC(GPP_H23, NONE),
 342
 343         /* R0 : GPP_R0 ==> HDA_BCLK */
 344         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
 345         /* R1 : GPP_R1 ==> HDA_SYNC */
 346         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
 347         /* R2 : GPP_R2 ==> HDA_SDO (PIN STRAP, Flash Descriptor Security Override */
 348         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
 349         /* R3 : GPP_R3 ==> HDA_SDIO */
 350         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
 351         /* R4 : GPP_R4 ==> HDA_RST# */
 352         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
 353         /* R5 : GPP_R5 ==> NC */
 354         PAD_NC(GPP_R5, NONE),
 355         /* R6 : GPP_R6 ==> SD_PWR_EN1 */
 356         PAD_CFG_GPO(GPP_R6, 0, PLTRST),
 357         /* R7 : GPP_R7 ==> SD_PWR_EN2 */
 358         PAD_CFG_GPO(GPP_R7, 0, PLTRST),
 359
 360         /* S0 : GPP_S0 ==> NC */
 361         PAD_NC(GPP_S0, NONE),
 362         /* S1 : GPP_S1 ==> NC */
 363         PAD_NC(GPP_S1, NONE),
 364         /* S2 : GPP_S2 ==> NC */
 365         PAD_NC(GPP_S2, NONE),
 366         /* S3 : GPP_S3 ==> NC */
 367         PAD_NC(GPP_S3, NONE),
 368         /* S4 : GPP_S4 ==> NC */
 369         PAD_NC(GPP_S4, NONE),
 370         /* S5 : GPP_S5 ==> NC */
 371         PAD_NC(GPP_S5, NONE),
 372         /* S6 : GPP_S6 ==> NC */
 373         PAD_NC(GPP_S6, NONE),
 374         /* S7 : GPP_S7 ==> NC */
 375         PAD_NC(GPP_S7, NONE),
 376
 377         /* GPD0: GPD0 ==> PCH_BATLOW# */
 378         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 379         /* GPD1: GPD1 ==> AC_PRESENT */
 380         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 381         /* GPD2: GPD2 ==> LAN_WAKE# */
 382         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 383         /* GPD3: GPD3 ==> SIO_PWRBTN# */
 384         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 385         /* GPD4: GPD4 ==> SIO_SLP_S3# */
 386         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 387         /* GPD5: GPD5 ==> SIO_SLP_S4# */
 388         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 389         /* GPD6: GPD6 ==> SIO_SLP_A# */
 390         PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 391         /* GPD7: GPD7 ==> PCH_TBT_PERST# (PIN STRAP, Reserved) */
 392         PAD_CFG_GPO(GPD7, 0, PLTRST),
 393         /* GPD8: GPD8 ==> SUSCLK */
 394         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 395         /* GPD9: GPD9 ==> SIO_SLP_WLAN# */
 396         PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 397         /* GPD10: GPD10 ==> SIO_SLP_S5# */
 398         PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 399         /* GPD11: GPD11 ==> PM_LANPHY_EN */
 400         PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 401 };
 402
 403 const struct pad_config *__weak variant_base_gpio_table(size_t *num)
 404 {
 405         *num = ARRAY_SIZE(gpio_table);
 406         return gpio_table;
 407 }
 408
 409 /* GPIO pads configured in bootblock */
 410 static const struct pad_config early_gpio_table[] = {
 411         /* A23 : GPP_A23 ==> RECOVERY# */
 412         PAD_CFG_GPI(GPP_A23, NONE, DEEP),
 413         /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
 414         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 415         /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
 416         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 417         /* C22 : GPP_C22 ==> H1_FLASH_WP */
 418         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 419         /* C23 : GPP_C23 ==> H1_PCH_INT# */
 420         PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
 421         /* E3  : GPP_E3 ==> MEM_INTERLEAVED */
 422         PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
 423         /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
 424         PAD_CFG_GPI(GPP_F11, NONE, DEEP),
 425         /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
 426         PAD_CFG_GPI(GPP_F12, NONE, DEEP),
 427         /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
 428         PAD_CFG_GPI(GPP_F13, NONE, DEEP),
 429         /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
 430         PAD_CFG_GPI(GPP_F14, NONE, DEEP),
 431         /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
 432         PAD_CFG_GPI(GPP_F15, NONE, DEEP),
 433         /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
 434         PAD_CFG_GPO(GPP_F16, 0, DEEP),
 435         /* H4  : GPP_H4 ==> DDR_CHA_EN_1P8 */
 436         PAD_CFG_GPI(GPP_H4, NONE, DEEP),
 437         /* H5  : GPP_H5 ==> DDR_CHB_EN_1P8 */
 438         PAD_CFG_GPI(GPP_H5, NONE, DEEP),
 439         /* H8  : GPP_H8 ==> I2C_SDA_PCH_H1 */
 440         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 441         /* H9  : GPP_H9 ==> I2C_SCL_PCH_H1 */
 442         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 443         /* GPD3: GPD3 ==> SIO_PWRBTN# */
 444         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 445 };
 446
 447 static const struct cros_gpio cros_gpios[] = {
 448         CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME),
 449         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME),
 450 };
 451
 452 const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
 453 {
 454         *num = ARRAY_SIZE(cros_gpios);
 455         return cros_gpios;
 456 }
 457
 458 /* Weak implementation of overrides */
 459 const struct pad_config *__weak variant_override_gpio_table(size_t *num)
 460 {
 461         *num = 0;
 462         return NULL;
 463 }
 464
 465 /* Weak implementation of early gpio */
 466 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
 467 {
 468         *num = ARRAY_SIZE(early_gpio_table);
 469         return early_gpio_table;
 470 }
 471
 472 int __weak has_360_sensor_board(void)
 473 {
 474         return 0;
 475 }