src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h

   1 /**
   2 Copyright (c) 2019-2020, Intel Corporation. All rights reserved.<BR>
   3
   4 Redistribution and use in source and binary forms, with or without modification,
   5 are permitted provided that the following conditions are met:
   6
   7 * Redistributions of source code must retain the above copyright notice, this
   8   list of conditions and the following disclaimer.
   9 * Redistributions in binary form must reproduce the above copyright notice, this
  10   list of conditions and the following disclaimer in the documentation and/or
  11   other materials provided with the distribution.
  12 * Neither the name of Intel Corporation nor the names of its contributors may
  13   be used to endorse or promote products derived from this software without
  14   specific prior written permission.
  15
  16   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  20   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26   THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 **/
  29
  30
  31 #ifndef _MEMORY_MAP_GUID_H_
  32 #define _MEMORY_MAP_GUID_H_
  33
  34 #define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \
  35         0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \
  36         0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \
  37         }
  38
  39 #define MEMTYPE_1LM_MASK       (1 << 0)
  40 #define MEMTYPE_2LM_MASK       (1 << 1)
  41 #define MEMTYPE_VOLATILE_MASK  (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
  42
  43 #define MAX_FPGA_REMOTE_SAD_RULES         2     // Maximum FPGA sockets exists on ICX platform
  44
  45 #define MAX_SAD_RULES                     24
  46 #define MAX_DRAM_CLUSTERS                 1
  47 #define MAX_IMC_PER_SOCKET                2
  48 #define MAX_SRAT_MEM_ENTRIES_PER_IMC      8
  49 #define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
  50         MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
  51         )
  52
  53 /* ACPI SRAT Memory Flags */
  54 #define SRAT_ACPI_MEMORY_ENABLED               (1 << 0)
  55 #define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED  (1 << 1)
  56 #define SRAT_ACPI_MEMORY_NONVOLATILE           (1 << 2)
  57
  58 #define MEM_TYPE_RESERVED (1 << 8)
  59 #define MEM_ADDR_64MB_SHIFT_BITS 26
  60
  61 #define NGN_MAX_SERIALNUMBER_STRLEN 4
  62 #define NGN_MAX_PARTNUMBER_STRLEN 20
  63 #define NGN_FW_VER_LEN 4
  64 //
  65 //  System Memory Map HOB information
  66 //
  67
  68 #pragma pack(1)
  69
  70 typedef struct SystemMemoryMapElement {
  71         // Type of this memory element; Bit0: 1LM  Bit1: 2LM  Bit2: PMEM  Bit3: PMEM-cache
  72         // Bit4: BLK Window  Bit5: CSR/Mailbox/Ctrl region
  73         UINT16   Type;
  74         // Node ID of the HA Owning the memory
  75         UINT8    NodeId;
  76         // Socket Id of socket that has his memory - ONLY IN NUMA
  77         UINT8    SocketId;
  78         // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
  79         UINT8    SktInterBitmap;
  80         // IMC interleave bitmap for this memory
  81         UINT8    ImcInterBitmap;
  82         // Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved;
  83         // 011b denotes Ch1 & 0 are interleaved
  84         UINT8    ChInterBitmap[MAX_IMC];
  85         // Base Address of the element in 64MB chunks
  86         UINT32   BaseAddress;
  87         // Size of this memory element in 64MB chunks
  88         UINT32   ElementSize;
  89 } SYSTEM_MEMORY_MAP_ELEMENT;
  90
  91 typedef struct DimmDevice {
  92         UINT8    Present;
  93         UINT8    reserved1[1];
  94         UINT8    DcpmmPresent;
  95         UINT8    reserved2[1];
  96         UINT8    NumRanks;
  97         UINT8    reserved3[1];
  98         UINT8    actKeyByte2;
  99         UINT8    reserved4[4];
 100         UINT16   nonVolCap;
 101         UINT16   DimmSize;
 102         UINT8    reserved5[4];
 103         UINT16   SPDMMfgId;                                 // Module Mfg Id from SPD
 104         UINT16   VendorID;
 105         UINT16   DeviceID;
 106         UINT8    reserved6[22];
 107         UINT8    serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
 108         UINT8    PartNumber[NGN_MAX_PARTNUMBER_STRLEN];     // Part Number
 109         UINT8    FirmwareVersionStr[NGN_FW_VER_LEN];        // Used to update the SMBIOS TYPE 17
 110         UINT8    reserved7[23];
 111         UINT16   SubsystemVendorID;
 112         UINT16   SubsystemDeviceID;
 113         UINT8    reserved8[4];
 114         UINT8    DimmSku;                                   // Dimm SKU info
 115         UINT8    reserved9[3];
 116         INT32    commonTck;
 117         UINT8    EnergyType;
 118         UINT8    reserved10[1];
 119         UINT16   SPDRegVen;                                 // Register Vendor ID in SPD
 120 } MEMMAP_DIMM_DEVICE_INFO_STRUCT;
 121
 122 struct ChannelDevice {
 123         UINT8    reserved1[15];
 124         MEMMAP_DIMM_DEVICE_INFO_STRUCT    DimmInfo[MAX_IMC];
 125 };
 126
 127 typedef struct socket {
 128         UINT8    reserved1[1114];
 129         struct   ChannelDevice ChannelInfo[MAX_CH];
 130 } MEMMAP_SOCKET;
 131
 132 /* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */
 133 typedef struct SystemMemoryMapHob {
 134   UINT8    reserved1[61];
 135
 136   UINT32   lowMemBase;                            // Mem base in 64MB units for below 4GB mem.
 137   UINT32   lowMemSize;                            // Mem size in 64MB units for below 4GB mem.
 138   UINT32   highMemBase;                           // Mem base in 64MB units for above 4GB mem.
 139   UINT32   highMemSize;                           // Mem size in 64MB units for above 4GB mem.
 140   UINT32   memSize;                               // Total physical memory size
 141   UINT16   memFreq;                               // Mem Frequency
 142
 143   UINT8    reserved2[22];
 144
 145   UINT8    DdrVoltage;
 146   UINT8    reserved3[38];
 147   UINT8    NumChPerMC;
 148   UINT8    numberEntries;                         // Number of Memory Map Elements
 149   SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
 150   UINT8    reserved4[2216];
 151   MEMMAP_SOCKET Socket[MAX_SOCKET];
 152   UINT8    reserved5[1603];
 153
 154   UINT16  BiosFisVersion;                              // Firmware Interface Specification version currently supported by BIOS
 155
 156   UINT8    reserved6[24];
 157
 158   UINT32   MmiohBase;                                   // MMIOH base in 64MB granularity
 159
 160   UINT8    reserved7[5];
 161
 162 } SYSTEM_MEMORY_MAP_HOB;
 163
 164 #pragma pack()
 165
 166 #endif