1 chip soc
/intel
/apollolake
3 device cpu_cluster
0 on
7 register
"pcie_rp0_clkreq_pin" = "3" # wifi
/bt
8 register
"pcie_rp2_clkreq_pin" = "0" # SSD
10 # Integrated Sensor Hub
11 register
"integrated_sensor_hub_enable" = "0"
13 # EMMC TX DATA Delay
1#
14 #
0x1A[14:8] stands
for 26*125 = 3250 pSec delay
for HS400
15 #
0x1A[6:0] stands
for 26*125 = 3250 pSec delay
for SDR104
/HS200
16 register
"emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
19 device pci
00.0 on
end #
- Host Bridge
20 device pci
00.1 on
end #
- DPTF
21 device pci
00.2 on
end #
- NPK
22 device pci
02.0 on
end #
- Gen
23 device pci
03.0 on
end #
- Iunit
24 device pci
0d
.0 on
end #
- P2SB
25 device pci
0d
.1 on
end #
- PMC
26 device pci
0d
.2 on
end #
- SPI
27 device pci
0d
.3 on
end #
- Shared SRAM
28 device pci
0e
.0 on
end #
- Audio
29 device pci
11.0 on
end #
- ISH
30 device pci
12.0 on
end #
- SATA
31 device pci
13.0 on
end #
- PCIe
-A
0
32 device pci
13.2 on
end #
- Onboard Lan
33 device pci
13.3 on
end #
- PCIe
-A
3
34 device pci
14.0 on
end #
- PCIe
-B
0
35 device pci
14.1 on
end #
- Onboard M2 Slot
(Wifi
/BT
)
36 device pci
15.0 on
end #
- XHCI
37 device pci
15.1 off
end #
- XDCI
38 device pci
16.0 on
end #
- I2C
0
39 device pci
16.1 on
end #
- I2C
1
40 device pci
16.2 on
end #
- I2C
2
41 device pci
16.3 on
end #
- I2C
3
42 device pci
17.0 on
end #
- I2C
4
43 device pci
17.1 on
end #
- I2C
5
44 device pci
17.2 on
end #
- I2C
6
45 device pci
17.3 on
end #
- I2C
7
46 device pci
18.0 on
end #
- UART
0
47 device pci
18.1 on
end #
- UART
1
48 device pci
18.2 on
end #
- UART
2
49 device pci
18.3 on
end #
- UART
3
50 device pci
19.0 on
end #
- SPI
0
51 device pci
19.1 on
end #
- SPI
1
52 device pci
19.2 on
end #
- SPI
2
53 device pci
1a
.0 on
end #
- PWM
54 device pci
1b
.0 on
end #
- SDCARD
55 device pci
1c
.0 on
end #
- eMMC
56 device pci
1e
.0 off
end #
- SDIO
57 device pci
1f
.0 on #
- LPC
58 chip ec
/google
/chromeec
59 device pnp
0c09.0 on
end
62 device pci
1f
.1 on
end #
- SMBUS
