2 ## This file is part of the coreboot project.
5 ## SPDX-License-Identifier: GPL-2.0-only
7 ifeq ($(CONFIG_SOC_QC_IPQ806X),y)
11 bootblock-$(CONFIG_SPI_FLASH) += spi.c
12 bootblock-y += timer.c
25 romstage-y += blobs_init.c
27 romstage-$(CONFIG_SPI_FLASH) += spi.c
35 ramstage-y += blobs_init.c
40 ramstage-$(CONFIG_SPI_FLASH) += spi.c
42 ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk
44 ramstage-y += tz_wrapper.S
50 ifeq ($(CONFIG_USE_BLOBS),y)
52 # Add MBN header to allow SBL3 to start coreboot bootblock
53 $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
54 @printf " ADD MBN $(subst $(obj)/,,$(@))\n"
55 ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
58 # Create a complete bootblock which will start up the system
59 $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
60 $(objcbfs)/bootblock.mbn
61 @printf " MBNCAT $(subst $(obj)/,,$(@))\n"
62 @util/qualcomm/mbncat.py -o $@.tmp $^
67 CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
69 # List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
70 mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
72 # Location of the binary blobs
73 mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x
75 # Create make variables to aid cbfs-files-handler in processing the blobs (add
76 # them all as raw binaries at the root level).
77 $(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\
78 $(eval $(f)-file := $(mbn-root)/$(f))\
79 $(eval $(f)-type := raw))