2 ## This file is part of the coreboot project.
5 ## SPDX-License-Identifier: GPL-2.0-only
7 ifeq ($(CONFIG_SOC_QC_IPQ40XX),y)
11 bootblock-$(CONFIG_SPI_FLASH) += spi.c
12 bootblock-y += timer.c
25 romstage-y += blobs_init.c
27 romstage-$(CONFIG_SPI_FLASH) += spi.c
35 ramstage-y += blobs_init.c
40 ramstage-$(CONFIG_SPI_FLASH) += spi.c
42 ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk
44 ramstage-y += tz_wrapper.S
51 ifeq ($(CONFIG_USE_BLOBS),y)
53 $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \
54 $(objcbfs)/bootblock.elf
55 @printf " CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n"
56 @$(CONFIG_SBL_UTIL_PATH)/createxbl.py -f $(CONFIG_SBL_ELF) \
57 -s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32
61 CPPFLAGS_common += -Isrc/soc/qualcomm/ipq40xx/include
63 # List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
64 mbn-files := $(CONFIG_CDT_MBN) $(CONFIG_DDR_MBN) $(CONFIG_TZ_MBN)
66 # Location of the binary blobs
67 mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq40xx
69 # Create make variables to aid cbfs-files-handler in processing the blobs (add
70 # them all as raw binaries at the root level).
71 $(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\
72 $(eval $(f)-file := $(mbn-root)/$(f))\
73 $(eval $(f)-type := raw))