2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
10 subdirs-y += ../../../cpu/x86/mtrr
11 subdirs-y += ../../../cpu/x86/tsc
13 bootblock-y += bootblock/esram_init.S
14 bootblock-y += bootblock/bootblock.c
16 bootblock-y += reg_access.c
17 bootblock-y += tsc_freq.c
18 bootblock-y += uart_common.c
21 verstage-y += reg_access.c
22 verstage-y += tsc_freq.c
23 verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
26 romstage-y += memmap.c
27 romstage-y += reg_access.c
28 romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
29 romstage-y += tsc_freq.c
30 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
33 postcar-y += fsp_params.c
35 postcar-y += reg_access.c
36 postcar-y += tsc_freq.c
37 postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
39 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
42 ramstage-y += fsp_params.c
43 ramstage-y += gpio_i2c.c
46 ramstage-y += northcluster.c
47 ramstage-y += reg_access.c
51 ramstage-y += spi_debug.c
52 ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
53 ramstage-y += tsc_freq.c
54 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
55 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
57 CPPFLAGS_common += -I$(src)/soc/intel/quark
58 CPPFLAGS_common += -I$(src)/soc/intel/quark/include
59 CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
61 # Chipset microcode path
62 CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
64 # Since FSP-M runs in CAR we need to relocate it to a specific address
65 $(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC)
67 # Add the FSP binary to the CBFS image
68 cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
69 fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
70 fsp.bin-position := $(CONFIG_FSP_LOC)
73 # Add the chipset microcode file to the CBFS image
74 cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
75 rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
76 rmu.bin-position := $(CONFIG_RMU_LOC)
79 endif # CONFIG_SOC_INTEL_QUARK