src/mainboard/sapphire/pureplatinumh61/cmos.layout

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## SPDX-License-Identifier: GPL-2.0-only
   6
   7 # -----------------------------------------------------------------
   8 entries
   9
  10 # -----------------------------------------------------------------
  11 # Status Register A
  12 # -----------------------------------------------------------------
  13 # Status Register B
  14 # -----------------------------------------------------------------
  15 # Status Register C
  16 #96           4       r       0        status_c_rsvd
  17 #100          1       r       0        uf_flag
  18 #101          1       r       0        af_flag
  19 #102          1       r       0        pf_flag
  20 #103          1       r       0        irqf_flag
  21 # -----------------------------------------------------------------
  22 # Status Register D
  23 #104          7       r       0        status_d_rsvd
  24 #111          1       r       0        valid_cmos_ram
  25 # -----------------------------------------------------------------
  26 # Diagnostic Status Register
  27 #112          8       r       0        diag_rsvd1
  28
  29 # -----------------------------------------------------------------
  30 0          120       r       0        reserved_memory
  31 #120        264       r       0        unused
  32
  33 # -----------------------------------------------------------------
  34 # RTC_BOOT_BYTE (coreboot hardcoded)
  35 384          1       e       4        boot_option
  36 388          4       h       0        reboot_counter
  37 #390          2       r       0        unused
  38
  39 # -----------------------------------------------------------------
  40 # coreboot config options: console
  41 #392          3       r       0        unused
  42 395          4       e       6        debug_level
  43 #399          1       r       0        unused
  44
  45 400          8       h       0        volume
  46
  47 # coreboot config options: southbridge
  48 408          1       e       1        nmi
  49 409          2       e       7        power_on_after_fail
  50
  51 #411       10       r       0        unused
  52 421         1       e       9        sata_mode
  53 #422        2       r       0        unused
  54
  55 # coreboot config options: cpu
  56 424          1       e       2        hyper_threading
  57 #425        7       r       0        unused
  58
  59 # coreboot config options: northbridge
  60 432         3        e      11        gfx_uma_size
  61 #435        549       r       0        unused
  62
  63 # SandyBridge MRC Scrambler Seed values
  64 896         32        r       0        mrc_scrambler_seed
  65 928         32        r       0        mrc_scrambler_seed_s3
  66 960         16        r       0        mrc_scrambler_seed_chk
  67
  68 # coreboot config options: check sums
  69 984         16       h       0        check_sum
  70
  71 # -----------------------------------------------------------------
  72
  73 enumerations
  74
  75 #ID value   text
  76 1     0     Disable
  77 1     1     Enable
  78 2     0     Enable
  79 2     1     Disable
  80 4     0     Fallback
  81 4     1     Normal
  82 6     0     Emergency
  83 6     1     Alert
  84 6     2     Critical
  85 6     3     Error
  86 6     4     Warning
  87 6     5     Notice
  88 6     6     Info
  89 6     7     Debug
  90 6     8     Spew
  91 7     0     Disable
  92 7     1     Enable
  93 7     2     Keep
  94 9     0     AHCI
  95 9     1     IDE
  96 11    0     32M
  97 11    1     64M
  98 11    2     96M
  99 11    3     128M
 100 11    4     160M
 101 11    5     192M
 102 11    6     224M
 103
 104 # -----------------------------------------------------------------
 105 checksums
 106
 107 checksum 392 415 984