src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / roda / rk9 / cmos.layout
blob688d102819dc4b22687c3577ef8d764d34c4ed21
2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 # -----------------------------------------------------------------
8 entries
10 # -----------------------------------------------------------------
11 # Status Register A
12 # -----------------------------------------------------------------
13 # Status Register B
14 # -----------------------------------------------------------------
15 # Status Register C
16 #96           4       r       0        status_c_rsvd
17 #100          1       r       0        uf_flag
18 #101          1       r       0        af_flag
19 #102          1       r       0        pf_flag
20 #103          1       r       0        irqf_flag
21 # -----------------------------------------------------------------
22 # Status Register D
23 #104          7       r       0        status_d_rsvd
24 #111          1       r       0        valid_cmos_ram
25 # -----------------------------------------------------------------
26 # Diagnostic Status Register
27 #112          8       r       0        diag_rsvd1
29 # -----------------------------------------------------------------
30 0           120       r       0        reserved_memory
31 #120        264       r       0        unused
33 # -----------------------------------------------------------------
34 # RTC_BOOT_BYTE (coreboot hardcoded)
35 384           1       e       4        boot_option
36 388           4       h       0        reboot_counter
37 #390          2       r       0        unused?
39 # -----------------------------------------------------------------
40 # coreboot config options: console
41 #392           3       r       0        unused
42 395           4       e       6        debug_level
43 #399          1       r       0        unused
45 # coreboot config options: cpu
46 #400          8       r       0        unused
48 # coreboot config options: southbridge
49 408           1       e       9        sata_mode
50 #409          7       r       0        unused
52 # coreboot config options: bootloader
53 416         512       s       0        boot_devices
54 928           8       h       0        boot_default
55 936           1       e       8        cmos_defaults_loaded
56 #937          7       r       0        unused
58 # coreboot config options: check sums
59 984          16       h       0        check_sum
61 # coreboot config options: northbridge
62 1000         4       e       10       gfx_uma_size
64 #1004        20       r       0        unused
66 # RAM initialization internal data
67 1024        128       r       0        read_training_results
69 # -----------------------------------------------------------------
71 enumerations
73 #ID value   text
74 1     0     Disable
75 1     1     Enable
76 2     0     Enable
77 2     1     Disable
78 4     0     Fallback
79 4     1     Normal
80 6     0     Emergency
81 6     1     Alert
82 6     2     Critical
83 6     3     Error
84 6     4     Warning
85 6     5     Notice
86 6     6     Info
87 6     7     Debug
88 6     8     Spew
89 7     0     Disable
90 7     1     Enable
91 7     2     Keep
92 8     0     No
93 8     1     Yes
94 9     0     AHCI
95 9     1     Compatible
96 11    4     32M
97 11    5     48M
98 11    6     64M
99 11    7     128M
100 11    8     256M
101 11    9     96M
102 11    10     160M
103 11    11     224M
104 11    12     352M
105 # -----------------------------------------------------------------
106 checksums
108 checksum 392 983 984