2 # This file is part of the coreboot project.
5 # SPDX
-License
-Identifier
: GPL
-2.0-only
7 chip northbridge
/amd
/pi/00730F01
/root_complex
8 device cpu_cluster
0 on
9 chip cpu
/amd
/pi/00730F01
15 subsystemid
0x1022 0x1410 inherit
17 chip northbridge
/amd
/pi/00730F01
18 device pci
0.0 on
end # Root Complex
19 device pci
0.2 on
end # IOMMU
20 device pci
1.0 off
end # Internal Graphics P2P bridge
0x9804
21 device pci
1.1 off
end # Internal Multimedia
22 device pci
2.0 on
end # PCIe Host Bridge
23 device pci
2.1 on
end # LAN1
24 device pci
2.2 on
end # LAN2
25 device pci
2.3 on
end # LAN3
26 device pci
2.4 on
end # LAN4
27 device pci
2.5 on
end # mPCIe slot
1
28 device pci
8.0 on
end # Platform Security Processor
29 end #chip northbridge
/amd
/pi/00730F01
31 chip southbridge
/amd
/pi/hudson
32 device pci
10.0 on
end # XHCI HC0 muxed with EHCI
2
33 device pci
11.0 on
end # SATA
34 device pci
12.0 on
end # USB EHCI0 usb
[0:3] is connected
35 device pci
13.0 on
end # USB EHCI1 usb
[4:7]
36 device pci
14.0 on
end # SM
37 device pci
14.3 on # LPC
0x439d
38 chip superio
/nuvoton
/nct5104d # SIO NCT5104D
39 register
"irq_trigger_type" = "0"
40 register
"reset_gpios" = "1"
41 device pnp
2e
.0 off
end
51 # UART C is conditionally turned on
56 # UART D is conditionally turned on
60 device pnp
2e
.008 off
end
64 # GPIO0
and GPIO1 are conditionally turned on
65 device pnp
2e
.007 on
end
66 device pnp
2e
.107 on
end
67 device pnp
2e
.607 off
end
68 device pnp
2e.f on
end
72 device pci
14.7 on
end # SD
73 device pci
16.0 on
end # USB EHCI2 usb
[8:7] - muxed with XHCI
74 end #chip southbridge
/amd
/pi/hudson
76 device pci
18.0 on
end
77 device pci
18.1 on
end
78 device pci
18.2 on
end
79 device pci
18.3 on
end
80 device pci
18.4 on
end
81 device pci
18.5 on
end
84 end #northbridge
/amd
/pi/00730F01
/root_complex