src/mainboard/msi/ms7721/cmos.layout

   1 #*****************************************************************************
   2 #
   3 #  This file is part of the coreboot project.
   4 #
   5 #
   6 # SPDX-License-Identifier: GPL-2.0-only
   7
   8 #*****************************************************************************
   9
  10 entries
  11
  12 0          384       r       0        reserved_memory
  13 384          1       e       4        boot_option
  14 388          4       h       0        reboot_counter
  15 #392          3       r       0        unused
  16 395          1       e       1        hw_scrubber
  17 396          1       e       1        interleave_chip_selects
  18 397          2       e       8        max_mem_clock
  19 399          1       e       2        multi_core
  20 400          1       e       1        power_on_after_fail
  21 412          4       e       6        debug_level
  22 440          4       e       9        slow_cpu
  23 444          1       e       1        nmi
  24 445          1       e       1        iommu
  25 456          1       e       1        ECC_memory
  26 728        256       h       0        user_data
  27 984         16       h       0        check_sum
  28 # Reserve the extended AMD configuration registers
  29 1000        24       r       0        amd_reserved
  30
  31 enumerations
  32
  33 #ID value   text
  34 1     0     Disable
  35 1     1     Enable
  36 2     0     Enable
  37 2     1     Disable
  38 4     0     Fallback
  39 4     1     Normal
  40 6     5     Notice
  41 6     6     Info
  42 6     7     Debug
  43 6     8     Spew
  44 8     0     400Mhz
  45 8     1     333Mhz
  46 8     2     266Mhz
  47 8     3     200Mhz
  48 9     0     off
  49 9     1     87.5%
  50 9     2     75.0%
  51 9     3     62.5%
  52 9     4     50.0%
  53 9     5     37.5%
  54 9     6     25.0%
  55 9     7     12.5%
  56
  57 checksums
  58
  59 checksum 392 983 984