2 ## This file is part of the coreboot project.
5 ## SPDX
-License
-Identifier
: GPL
-2.0-only
7 chip northbridge
/intel
/ironlake
9 register
"gfx" = "GMA_STATIC_DISPLAYS(1)"
12 # Enable DisplayPort Hotplug with
6ms pulse
13 register
"gpu_dp_d_hotplug" = "0x06"
15 # Enable Panel
as LVDS
and configure power delays
16 register
"gpu_panel_port_select" = "0" # LVDS
17 register
"gpu_panel_power_cycle_delay" = "3"
18 register
"gpu_panel_power_up_delay" = "250"
19 register
"gpu_panel_power_down_delay" = "250"
20 register
"gpu_panel_power_backlight_on_delay" = "2500"
21 register
"gpu_panel_power_backlight_off_delay" = "2500"
22 register
"gpu_cpu_backlight" = "0x58d"
23 register
"gpu_pch_backlight" = "0x061a061a"
25 device cpu_cluster
0 on
26 chip cpu
/intel
/model_2065x
31 register
"pci_mmio_size" = "1024"
34 device pci
00.0 on # Host bridge
35 subsystemid
0x17aa 0x2193
37 device pci
01.0 off
end # PEG
38 device pci
02.0 on # VGA controller
39 subsystemid
0x17aa 0x215a
41 chip southbridge
/intel
/ibexpeak
43 #
0 No effect
(default
)
44 #
1 SMI#
(if corresponding ALT_GPI_SMI_EN bit is also
set)
45 #
2 SCI
(if corresponding GPIO_EN bit is also
set)
46 register
"gpi1_routing" = "2"
47 register
"gpi13_routing" = "2"
49 register
"sata_port_map" = "0x03"
51 register
"gpe0_en" = "0x20022046"
52 register
"alt_gp_smi_en" = "0x0000"
53 register
"gen1_dec" = "0x7c1601"
54 register
"gen2_dec" = "0x0c15e1"
55 register
"gen3_dec" = "0x1c1681"
56 register
"gen4_dec" = "0x040069"
58 register
"c2_latency" = "1"
59 register
"docking_supported" = "1"
61 register
"pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
63 device pci
16.0 on
end # Management Engine Interface
1
64 device pci
16.1 off
end # Management Engine Interface
2
65 device pci
16.2 off
end # Management Engine IDE
-R
, only management boot
66 device pci
16.3 off
end # Management Engine KT
68 device pci
19.0 on # Ethernet
69 subsystemid
0x17aa 0x2153
72 device pci
1a
.0 on # USB2 EHCI
73 subsystemid
0x17aa 0x2163
76 device pci
1b
.0 on # Audio Controller
77 subsystemid
0x17aa 0x215e
80 device pci
1c
.0 on
end # PCIe Port #
1
81 device pci
1c
.1 on
end # PCIe Port #
2 (wwan
)
82 device pci
1c
.2 off
end
84 smbios_slot_desc
"7" "3" "ExpressCard Slot" "8"
85 end # PCIe Port #
4 (Expresscard
)
86 device pci
1c
.4 on
end # PCIe Port #
5 (wlan
)
87 device pci
1c
.5 off
end
88 device pci
1c
.6 off
end
89 device pci
1c
.7 off
end
91 device pci
1d
.0 on # USB2 EHCI
92 subsystemid
0x17aa 0x2163
94 device pci
1e
.0 on
end # PCI
2 PCI bridge
95 device pci
1f
.0 on # PCI
-LPC bridge
96 subsystemid
0x17aa 0x2166
97 chip superio
/nsc
/pc87382
98 device pnp
164e
.3 on # Digitizer
105 device pnp
164e
.2 off
end
106 # GPIO
, not connected
107 device pnp
164e
.7 off
end
108 # DLPC
, not connected
109 device pnp
164e
.19 off
end
111 chip drivers
/pc80
/tpm
112 device pnp
0c31.0 on
end
116 device pnp ff
.1 on
end # dummy
117 register
"backlight_enable" = "0x01"
118 register
"dock_event_enable" = "0x01"
122 device pnp ff
.2 on # dummy
129 register
"config0" = "0xa6"
130 register
"config1" = "0x05"
131 register
"config2" = "0xa0"
132 register
"config3" = "0x01"
134 register
"beepmask0" = "0xfe"
135 register
"beepmask1" = "0x96"
136 register
"has_power_management_beeps" = "1"
138 register
"event2_enable" = "0xff"
139 register
"event3_enable" = "0xff"
140 register
"event4_enable" = "0xf4"
141 register
"event5_enable" = "0x3c"
142 register
"event6_enable" = "0x80"
143 register
"event7_enable" = "0x01"
144 register
"event8_enable" = "0x01"
145 register
"event9_enable" = "0xff"
146 register
"eventa_enable" = "0xff"
147 register
"eventb_enable" = "0xff"
148 register
"eventc_enable" = "0xff"
149 register
"eventd_enable" = "0xff"
151 register
"has_bdc_detection" = "1"
152 register
"bdc_gpio_num" = "48"
153 register
"bdc_gpio_lvl" = "0"
156 device pci
1f
.2 on # IDE
/SATA
157 subsystemid
0x17aa 0x2168
159 device pci
1f
.3 on # SMBUS
160 subsystemid
0x17aa 0x2167
161 # eeprom
, 8 virtual devices
, same chip
162 chip drivers
/i2c
/at24rf08c
173 device pci
1f
.4 off
end
174 device pci
1f
.5 off
end
175 device pci
1f
.6 on
end