src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / jetway / nf81-t56n-lf / devicetree.cb
blobe7b74f7d38098e8df3944b7c7a20cd838e1e50de
2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 chip northbridge/amd/agesa/family14/root_complex
8 device cpu_cluster 0 on
9 chip cpu/amd/agesa/family14
10 device lapic 0 on end
11 end
12 end
13 device domain 0 on
14 subsystemid 0x1022 0x1510 inherit
15 chip northbridge/amd/agesa/family14
16 device pci 0.0 on end # Root Complex
17 device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
18 device pci 4.0 on end # PCIE P2P bridge PCIe slot
19 device pci 5.0 off end # PCIE P2P bridge
20 device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
21 device pci 7.0 off end # PCIE P2P bridge
22 device pci 8.0 off end # NB/SB Link P2P bridge
23 end # agesa northbridge
25 chip southbridge/amd/cimx/sb800
26 device pci 11.0 on end # SATA
27 device pci 12.0 on end # OHCI USB 0-4
28 device pci 12.2 on end # EHCI USB 0-4
29 device pci 13.0 on end # OHCI USB 5-9
30 device pci 13.2 on end # EHCI USB 5-9
31 device pci 14.0 on end # SM
32 device pci 14.1 off end # IDE 0x439c
33 device pci 14.2 on end # HDA 0x4383
34 device pci 14.3 on # LPC 0x439d
35 chip superio/fintek/f71869ad
36 register "multi_function_register_1" = "0x01"
37 register "multi_function_register_2" = "0x6f"
38 register "multi_function_register_3" = "0x24"
39 register "multi_function_register_4" = "0x00"
40 register "multi_function_register_5" = "0x60"
41 # HWM configuration registers
42 register "hwm_smbus_address" = "0x98"
43 register "hwm_smbus_control_reg" = "0x02"
44 register "hwm_fan_type_sel_reg" = "0x00"
45 register "hwm_fan1_temp_adj_rate_reg" = "0x33"
46 register "hwm_fan_mode_sel_reg" = "0x07"
47 register "hwm_fan1_idx_rpm_mode" = "0x0e"
48 register "hwm_fan1_seg1_speed_count" = "0xff"
49 register "hwm_fan1_seg2_speed_count" = "0x0e"
50 register "hwm_fan1_seg3_speed_count" = "0x07"
51 register "hwm_fan1_temp_map_sel" = "0x8c"
52 register "hwm_temp_sensor_type" = "0x0E" # default value
54 # XXX: 4e is the default index port and .xy is the
55 # LDN indexing the pnp_info array found in the superio.c
56 # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
57 # see page 18 from Fintek F71869 V1.1 datasheet.
58 device pnp 2e.00 off # Floppy
59 io 0x60 = 0x3f0
60 irq 0x70 = 6
61 drq 0x74 = 2
62 end
63 device pnp 2e.01 on # COM1
64 io 0x60 = 0x3f8
65 irq 0x70 = 4
66 end
67 # COM2 not physically wired on board.
68 device pnp 2e.02 off # COM2
69 io 0x60 = 0x2f8
70 irq 0x70 = 3
71 end
72 device pnp 2e.03 off # Parallel Port
73 io 0x60 = 0x378
74 irq 0x70 = 7
75 drq 0x74 = 3
76 end
77 device pnp 2e.04 on # Hardware Monitor
78 io 0x60 = 0x225 # Fintek datasheet says 0x295.
79 irq 0x70 = 0
80 end
81 device pnp 2e.05 on # KBC
82 io 0x60 = 0x060
83 irq 0x70 = 1 # Keyboard IRQ
84 irq 0x72 = 12 # Mouse IRQ
85 end
86 device pnp 2e.06 off end # GPIO
87 device pnp 2e.07 on end # WDT
88 device pnp 2e.08 off end # CIR
89 device pnp 2e.0a on end # PME
90 end # f71869ad
91 end #LPC
92 device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
93 device pci 14.5 on end # OHCI FS/LS USB (0x4399)
94 device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
95 device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
96 device pci 15.1 on end # PCIe PortB
97 device pci 15.2 off end # PCIe PortC
98 device pci 15.3 off end # PCIe PortD
99 device pci 16.0 on end # OHCI USB 10-13 (0x4397)
100 device pci 16.2 on end # EHCI USB 10-13 (0x4396)
101 register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes.
102 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
104 end #southbridge/amd/cimx/sb800
106 chip northbridge/amd/agesa/family14
108 # These seem unnecessary
109 device pci 18.0 on end
110 device pci 18.1 on end
111 device pci 18.2 on end
112 device pci 18.3 on end
113 device pci 18.4 on end
114 device pci 18.5 on end
115 device pci 18.6 on end
116 device pci 18.7 on end
119 # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
120 # with i2cdump tool.
121 # Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
123 register "spdAddrLookup" = "
125 { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
126 { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
129 end # agesa northbridge
131 end #domain
132 end #northbridge/amd/agesa/family14/root_complex