src/mainboard/intel/wtm2/cmos.layout

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## SPDX-License-Identifier: GPL-2.0-only
   6
   7 # -----------------------------------------------------------------
   8 entries
   9
  10 # -----------------------------------------------------------------
  11 # Status Register A
  12 # -----------------------------------------------------------------
  13 # Status Register B
  14 # -----------------------------------------------------------------
  15 # Status Register C
  16 #96           4       r       0        status_c_rsvd
  17 #100          1       r       0        uf_flag
  18 #101          1       r       0        af_flag
  19 #102          1       r       0        pf_flag
  20 #103          1       r       0        irqf_flag
  21 # -----------------------------------------------------------------
  22 # Status Register D
  23 #104          7       r       0        status_d_rsvd
  24 #111          1       r       0        valid_cmos_ram
  25 # -----------------------------------------------------------------
  26 # Diagnostic Status Register
  27 #112          8       r       0        diag_rsvd1
  28
  29 # -----------------------------------------------------------------
  30 0          120       r       0        reserved_memory
  31 #120        264       r       0        unused
  32
  33 # -----------------------------------------------------------------
  34 # RTC_BOOT_BYTE (coreboot hardcoded)
  35 384          1       e       4        boot_option
  36 388          4       h       0        reboot_counter
  37 #390          2       r       0        unused?
  38
  39 # -----------------------------------------------------------------
  40 # coreboot config options: console
  41 #392          3       r       0        unused
  42 395          4       e       6        debug_level
  43 #399          1       r       0        unused
  44
  45 # coreboot config options: cpu
  46 400          1       e       2        hyper_threading
  47 #401          7       r       0        unused
  48
  49 # coreboot config options: southbridge
  50 408          1       e       1        nmi
  51 409          2       e       7        power_on_after_fail
  52 #411          5       r       0        unused
  53
  54 # coreboot config options: bootloader
  55 #Used by ChromeOS:
  56 416        128       r        0        vbnv
  57 #544        440       r       0        unused
  58
  59 # SandyBridge MRC Scrambler Seed values
  60 896         32        r       0        mrc_scrambler_seed
  61 928         32        r       0        mrc_scrambler_seed_s3
  62
  63 # coreboot config options: check sums
  64 984         16       h       0        check_sum
  65 #1000        24       r       0        amd_reserved
  66
  67 # -----------------------------------------------------------------
  68
  69 enumerations
  70
  71 #ID value   text
  72 1     0     Disable
  73 1     1     Enable
  74 2     0     Enable
  75 2     1     Disable
  76 4     0     Fallback
  77 4     1     Normal
  78 6     0     Emergency
  79 6     1     Alert
  80 6     2     Critical
  81 6     3     Error
  82 6     4     Warning
  83 6     5     Notice
  84 6     6     Info
  85 6     7     Debug
  86 6     8     Spew
  87 7     0     Disable
  88 7     1     Enable
  89 7     2     Keep
  90 # -----------------------------------------------------------------
  91 checksums
  92
  93 checksum 392 415 984