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src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / intel / saddlebrook / devicetree.cb
blob2e82614b6b927ad88646d87be95ceab477c30900
1 ##
2 ## This file is part of the coreboot project.
3 ##
4 ##
5 ## SPDX-License-Identifier: GPL-2.0-only
6
7 chip soc/intel/skylake
8
9 register "deep_s5_enable_ac" = "0"
10 register "deep_s5_enable_dc" = "0"
11 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
12
13 # GPE configuration
14 # Note that GPE events called out in ASL code rely on this
15 # route. i.e. If this route changes then the affected GPE
16 # offset bits also need to be changed.
17 register "gpe0_dw0" = "GPP_B"
18 register "gpe0_dw1" = "GPP_D"
19 register "gpe0_dw2" = "GPP_E"
20
21 # Enable "Intel Speed Shift Technology"
22 register "speed_shift_enable" = "1"
23
24 # FSP Configuration
25 register "EnableAzalia" = "1"
26 register "DspEnable" = "1"
27 register "IoBufferOwnership" = "3"
28 register "SmbusEnable" = "1"
29 register "ScsEmmcEnabled" = "0"
30 register "ScsEmmcHs400Enabled" = "0"
31 register "ScsSdCardEnabled" = "0"
32 register "SkipExtGfxScan" = "1"
33 register "Device4Enable" = "0"
34 register "Heci3Enabled" = "0"
35
36 register "SaGv" = "SaGv_Enabled"
37 register "PmTimerDisabled" = "0"
38
39 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
40 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
41 register "PmConfigSlpS3MinAssert" = "0x02"
42
43 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
44 register "PmConfigSlpS4MinAssert" = "0x04"
45
46 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
47 register "PmConfigSlpSusMinAssert" = "0x03"
48
49 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
50 register "PmConfigSlpAMinAssert" = "0x03"
51
52 register "serirq_mode" = "SERIRQ_CONTINUOUS"
53
54 # Lock Down
55 register "common_soc_config" = "{
56 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
57 }"
58
59 # VR Settings Configuration for 4 Domains
60 #+----------------+-----------+-----------+-------------+----------+
61 #| Domain/Setting | SA | IA | GT Unsliced | GT |
62 #+----------------+-----------+-----------+-------------+----------+
63 #| Psi1Threshold | 20A | 20A | 20A | 20A |
64 #| Psi2Threshold | 4A | 5A | 5A | 5A |
65 #| Psi3Threshold | 1A | 1A | 1A | 1A |
66 #| Psi3Enable | 1 | 1 | 1 | 1 |
67 #| Psi4Enable | 1 | 1 | 1 | 1 |
68 #| ImonSlope | 0 | 0 | 0 | 0 |
69 #| ImonOffset | 0 | 0 | 0 | 0 |
70 #| IccMax | 7A | 34A | 35A | 35A |
71 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
72 #+----------------+-----------+-----------+-------------+----------+
73 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
74 .vr_config_enable = 1,
75 .psi1threshold = VR_CFG_AMP(20),
76 .psi2threshold = VR_CFG_AMP(4),
77 .psi3threshold = VR_CFG_AMP(1),
78 .psi3enable = 1,
79 .psi4enable = 1,
80 .imon_slope = 0x0,
81 .imon_offset = 0x0,
82 .icc_max = VR_CFG_AMP(7),
83 .voltage_limit = 1520,
84 }"
85
86 register "domain_vr_config[VR_IA_CORE]" = "{
87 .vr_config_enable = 1,
88 .psi1threshold = VR_CFG_AMP(20),
89 .psi2threshold = VR_CFG_AMP(5),
90 .psi3threshold = VR_CFG_AMP(1),
91 .psi3enable = 1,
92 .psi4enable = 1,
93 .imon_slope = 0x0,
94 .imon_offset = 0x0,
95 .icc_max = VR_CFG_AMP(34),
96 .voltage_limit = 1520,
97 }"
98
99 register "domain_vr_config[VR_GT_UNSLICED]" = "{
100 .vr_config_enable = 1,
101 .psi1threshold = VR_CFG_AMP(20),
102 .psi2threshold = VR_CFG_AMP(5),
103 .psi3threshold = VR_CFG_AMP(1),
104 .psi3enable = 1,
105 .psi4enable = 1,
106 .imon_slope = 0x0,
107 .imon_offset = 0x0,
108 .icc_max = VR_CFG_AMP(35),
109 .voltage_limit = 1520,
110 }"
111
112 register "domain_vr_config[VR_GT_SLICED]" = "{
113 .vr_config_enable = 1,
114 .psi1threshold = VR_CFG_AMP(20),
115 .psi2threshold = VR_CFG_AMP(5),
116 .psi3threshold = VR_CFG_AMP(1),
117 .psi3enable = 1,
118 .psi4enable = 1,
119 .imon_slope = 0x0,
120 .imon_offset = 0x0,
121 .icc_max = VR_CFG_AMP(35),
122 .voltage_limit = 1520,
123 }"
124
125 # Enable x1 slot
126 register "PcieRpEnable[7]" = "1"
127 register "PcieRpClkReqSupport[7]" = "1"
128 register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
129
130 # Enable x4 slot
131 register "PcieRpEnable[8]" = "1"
132 register "PcieRpClkReqSupport[8]" = "1"
133 register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
134
135 # Enable Root port 6 and 13.
136 register "PcieRpEnable[5]" = "1"
137 register "PcieRpEnable[12]" = "1"
138
139 # Enable CLKREQ#
140 register "PcieRpClkReqSupport[5]" = "1"
141 register "PcieRpClkReqSupport[12]" = "1"
142
143 # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
144 register "PcieRpClkReqNumber[5]" = "0"
145 register "PcieRpClkReqNumber[12]" = "1"
146
147 register "EnableLan" = "1"
148
149 # USB related
150 register "SsicPortEnable" = "1"
151
152 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
153 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
154 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
155 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
156 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
157 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
158 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
159 register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
160 register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
161 register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
162 register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
163 register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
164 register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
165 register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
166
167 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
168 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
169 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
170 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
171 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
172 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
173 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
174 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
175 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
176 register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
177
178 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
179
180 # Must leave UART0 enabled or SD/eMMC will not work as PCI
181
182 register "pirqa_routing" = "0x0b"
183 register "pirqb_routing" = "0x0a"
184 register "pirqc_routing" = "0x0b"
185 register "pirqd_routing" = "0x0b"
186 register "pirqe_routing" = "0x0b"
187 register "pirqf_routing" = "0x0b"
188 register "pirqg_routing" = "0x0b"
189 register "pirqh_routing" = "0x0b"
190
191 register "PmTimerDisabled" = "0"
192
193 register "EnableSata" = "1"
194 register "SataSalpSupport" = "1"
195 register "SataPortsEnable" = "{ \
196 [0] = 1, \
197 [1] = 1, \
198 [2] = 1, \
199 [3] = 1, \
200 [4] = 1, \
201 [5] = 1, \
202 [6] = 1, \
203 [7] = 1, \
204 }"
205 register "SerialIoDevMode" = "{ \
206 [PchSerialIoIndexI2C0] = PchSerialIoPci, \
207 [PchSerialIoIndexI2C1] = PchSerialIoPci, \
208 [PchSerialIoIndexI2C2] = PchSerialIoPci, \
209 [PchSerialIoIndexI2C3] = PchSerialIoPci, \
210 [PchSerialIoIndexI2C4] = PchSerialIoPci, \
211 [PchSerialIoIndexI2C5] = PchSerialIoPci, \
212 [PchSerialIoIndexSpi0] = PchSerialIoPci, \
213 [PchSerialIoIndexSpi1] = PchSerialIoPci, \
214 [PchSerialIoIndexUart0] = PchSerialIoPci, \
215 [PchSerialIoIndexUart1] = PchSerialIoPci, \
216 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
217 }"
218
219 # PL2 override 25W
220 register "tdp_pl2_override" = "25"
221
222 # Send an extra VR mailbox command for the PS4 exit issue
223 register "SendVrMbxCmd" = "2"
224
225 # Use default SD card detect GPIO configuration
226 #register "sdcard_cd_gpio_default" = "GPP_A7"
227
228 device cpu_cluster 0 on
229 device lapic 0 on end
230 end
231 device domain 0 on
232 device pci 00.0 on end # Host Bridge
233 device pci 02.0 on end # Integrated Graphics Device
234 device pci 14.0 on end # USB xHCI
235 device pci 14.1 off end # USB xDCI (OTG)
236 device pci 14.2 on end # Thermal Subsystem
237 device pci 15.0 on end # I2C #0
238 device pci 15.1 on end # I2C #1
239 device pci 15.2 on end # I2C #2
240 device pci 15.3 on end # I2C #3
241 device pci 16.0 on end # Management Engine Interface 1
242 device pci 16.1 off end # Management Engine Interface 2
243 device pci 16.2 off end # Management Engine IDE-R
244 device pci 16.3 off end # Management Engine KT Redirection
245 device pci 16.4 off end # Management Engine Interface 3
246 device pci 17.0 on end # SATA
247 device pci 19.0 on end # UART #2
248 device pci 19.1 on end # I2C #5
249 device pci 19.2 on end # I2C #4
250 device pci 1c.0 on end # PCI Express Port 1
251 device pci 1c.1 off end # PCI Express Port 2
252 device pci 1c.2 off end # PCI Express Port 3
253 device pci 1c.3 off end # PCI Express Port 4
254 device pci 1c.4 off end # PCI Express Port 5
255 device pci 1c.5 off end # PCI Express Port 6
256 device pci 1c.6 off end # PCI Express Port 7
257 device pci 1c.7 off end # PCI Express Port 8
258 device pci 1d.0 off end # PCI Express Port 9
259 device pci 1d.1 off end # PCI Express Port 10
260 device pci 1d.2 off end # PCI Express Port 11
261 device pci 1d.3 off end # PCI Express Port 12
262 device pci 1e.0 on end # UART #0
263 device pci 1e.1 on end # UART #1
264 device pci 1e.2 on end # GSPI #0
265 device pci 1e.3 on end # GSPI #1
266 device pci 1e.4 off end # eMMC
267 device pci 1e.5 off end # SDIO
268 device pci 1e.6 off end # SDCard
269 device pci 1f.0 on
270 end # LPC Interface
271 device pci 1f.1 on end # P2SB
272 device pci 1f.2 on end # Power Management Controller
273 device pci 1f.3 on end # Intel HDA
274 device pci 1f.4 on end # SMBus
275 device pci 1f.5 on end # PCH SPI
276 device pci 1f.6 on end # GbE
277 end
278 end
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