2 ## This file is part of the coreboot project.
5 ## SPDX
-License
-Identifier
: GPL
-2.0-only
7 chip northbridge
/intel
/sandybridge
8 register
"gfx.use_spread_spectrum_clock" = "0"
9 register
"gpu_dp_b_hotplug" = "0"
10 register
"gpu_dp_c_hotplug" = "0"
11 register
"gpu_dp_d_hotplug" = "0"
13 device cpu_cluster
0x0 on
14 chip cpu
/intel
/model_206ax
15 register
"c1_acpower" = "1"
16 register
"c1_battery" = "1"
17 register
"c2_acpower" = "3"
18 register
"c2_battery" = "3"
19 register
"c3_acpower" = "5"
20 register
"c3_battery" = "5"
21 device lapic
0x0 on
end
22 device lapic
0xacac off
end
26 register
"pci_mmio_size" = "2048"
29 subsystemid
0x103c 0x1791 inherit
31 device pci
00.0 on
end # Host bridge Host bridge
32 device pci
01.0 on
end # PCIe Bridge
for discrete graphics
33 device pci
02.0 on
end # Internal graphics VGA controller
35 chip southbridge
/intel
/bd82x6x # Intel Series
7 PCH
36 register
"c2_latency" = "0x0065"
37 register
"docking_supported" = "0"
38 register
"gen1_dec" = "0x00fc0601"
39 register
"gen2_dec" = "0x00fc0801"
40 register
"pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
41 register
"pcie_port_coalesce" = "1"
42 register
"sata_interface_speed_support" = "0x3"
43 register
"sata_port_map" = "0xf"
44 register
"spi_lvscc" = "0x2005"
45 register
"spi_uvscc" = "0x2005"
47 device pci
14.0 on
end # xHCI
48 device pci
16.0 on
end # Management Engine Interface
1
49 device pci
16.1 off
end # Management Engine Interface
2
50 device pci
16.2 off
end # Management Engine IDE
-R
51 device pci
16.3 on
end # Management Engine KT
52 device pci
19.0 on
end # Intel Gigabit Ethernet
53 device pci
1a
.0 on
end # USB2 EHCI #
2
54 device pci
1b
.0 on
end # High Definition Audio Audio controller
55 device pci
1c
.0 on
end # PCIe Port #
1
56 device pci
1c
.1 off
end # PCIe Port #
2
57 device pci
1c
.2 off
end # PCIe Port #
3
58 device pci
1c
.3 off
end # PCIe Port #
4
59 device pci
1c
.4 on
end # PCIe Port #
5
60 device pci
1c
.5 off
end # PCIe Port #
6
61 device pci
1c
.6 on
end # PCIe Port #
7
62 device pci
1c
.7 on
end # PCIe Port #
8
63 device pci
1d
.0 on
end # USB2 EHCI #
1
64 device pci
1e
.0 on
end # PCI bridge
65 device pci
1f
.0 on # LPC bridge PCI
-LPC bridge
67 device pnp
2e.ff on # passes SIO base addr
to SSDT gen
68 chip superio
/nuvoton
/npcd378
69 device pnp
2e
.0 off
end # Floppy
70 device pnp
2e
.1 on # Parallel port
73 # serialice
: Vendor writes
:
79 # dumped from superiotool
:
89 device pnp
2e
.2 off # COM1
93 device pnp
2e
.3 on # COM2
, IR
97 device pnp
2e
.4 on # LED
control
99 # IOBASE
[0h
] = bit0 LED red
/ green
100 # IOBASE
[0h
] = bit1
-4 LED PWM duty cycle
101 # IOBASE
[1h
] = bit6 SWCC
106 # IOBASE
[4h
:7h
] = 32bit upcounter at
1Mhz
107 # IOBASE
[8h
:bh
] = GPS
108 # IOBASE
[ch
:fh
] = GPE
110 device pnp
2e
.5 on # Mouse
113 device pnp
2e
.6 on # Keyboard
117 # serialice
: Vendor writes
:
120 device pnp
2e
.7 on # WDT ?
123 device pnp
2e
.8 on # HWM
125 # IOBASE
[0h
:feh
] HWM page
126 # IOBASE
[ffh
] bit0
-bit3 page selector
138 device pnp
2e.f on # GPIO OD ?
144 device pnp
2e
.15 on # BUS ?
148 device pnp
2e
.1c on # Suspend
Control ?
150 # writing
to IOBASE
[5h
]
152 #
0x9: Power off
and bricked until CMOS battery removed
154 device pnp
2e
.1e on # GPIO ?
157 # skip the following
, as it
158 # looks like remapped registers
166 chip drivers
/pc80
/tpm
167 device pnp
4e
.0 on
end # TPM module
170 device pci
1f
.2 on
end # SATA Controller
1
171 device pci
1f
.3 on
end # SMBus
172 device pci
1f
.5 off
end # SATA Controller
2
173 device pci
1f
.6 off
end # Thermal