src/mainboard/google/nyan/devicetree.cb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## SPDX-License-Identifier: GPL-2.0-only
   6
   7 chip soc/nvidia/tegra124
   8         device cpu_cluster 0 on end
   9 # N.B. We are not using the device tree in an effective way.
  10 # We need to change this in future such that the on-SoC
  11 # devices are 'chips', which will allow us to go at them
  12 # in parallel. This is even easier on the ARM SoCs since there
  13 # are no single-access resources such as the infamous
  14 # 0xcf8/0xcfc registers found on PCs.
  15         register "display_controller" = "TEGRA_ARM_DISPLAYA"
  16         register "xres" = "1366"
  17         register "yres" = "768"
  18
  19         # bits per pixel and color depth
  20         register "framebuffer_bits_per_pixel" = "16"
  21         register "color_depth" = "6"
  22         # "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
  23
  24         register "panel_bits_per_pixel" = "18"
  25
  26         # With some help from the mainbaord designer
  27         register "backlight_en_gpio" = "GPIO(H2)"
  28         register "lvds_shutdown_gpio" = "0"
  29         register "backlight_vdd_gpio" = "GPIO(P2)"
  30         register "panel_vdd_gpio" = "0"
  31         register "pwm" = "1"
  32
  33         # Various panel delay times
  34         register "vdd_delay_ms" = "200"
  35         register "pwm_to_bl_delay_ms" = "10"
  36         register "vdd_to_hpd_delay_ms" = "200"
  37         register "hpd_unplug_min_us" = "2000"
  38         register "hpd_plug_min_us" = "250"
  39         register "hpd_irq_min_us" = "250"
  40
  41 # How to compute these: xrandr --verbose will give you this:
  42 #Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
  43 #               2560 2608 2640 2720 hborder 0
  44 #               1700 1703 1713 1749 vborder 0
  45 #Then you can compute your values:
  46 #H front porch = 2608 - 2560 = 48
  47 #H sync = 2640 - 2608 = 32
  48 #H back porch = 2720 - 2640 = 80
  49 #V front porch = 1703 - 1700 = 3
  50 #V sync = 1713 - 1703 = 10
  51 #V back porch = 1749 - 1713 = 36
  52 #href_to_sync and vref_to_sync are from the vendor
  53 #this is just an example for a Pixel panel; other panels differ.
  54 # Here is a peppy panel:
  55 #  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
  56 #        h: width  1366 start 1502 end 1532 total 1592
  57 #        v: height  768 start  776 end  788 total  800
  58         register "href_to_sync" = "1"
  59         register "hfront_porch" = "136"
  60         register "hsync_width" = "30"
  61         register "hback_porch" = "60"
  62
  63         register "vref_to_sync" = "1"
  64         register "vfront_porch" = "8"
  65         register "vsync_width" = "12"
  66         register "vback_porch" = "12"
  67
  68         register "pixel_clock" = "76400000"
  69
  70         # link configurations
  71         register "lane_count" = "1"
  72         register "enhanced_framing" = "1"
  73         register "link_bw" = "10"
  74         # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
  75
  76         register "drive_current" = "0x40404040"
  77         register "preemphasis" = "0x0f0f0f0f"
  78         register "postcursor" = "0"
  79 end