src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / gizmosphere / gizmo / devicetree.cb
blob06237734ae2484587af69f2f6876884bedd7452b
2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 chip northbridge/amd/agesa/family14/root_complex
8 device cpu_cluster 0 on
9 chip cpu/amd/agesa/family14
10 device lapic 0 on end
11 end
12 end
13 device domain 0 on
14 subsystemid 0x1022 0x1510 inherit
15 chip northbridge/amd/agesa/family14 # CPU side of HT root complex
16 chip northbridge/amd/agesa/family14 # PCI side of HT root complex
17 device pci 0.0 on end # Root Complex
18 device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
19 device pci 4.0 off end # PCIE P2P bridge 0x9604
20 device pci 5.0 on end # PCIE P2P bridge 0x9605
21 device pci 6.0 off end # PCIE P2P bridge 0x9606
22 device pci 7.0 off end # PCIE P2P bridge 0x9607
23 device pci 8.0 off end # NB/SB Link P2P bridge
24 end # agesa northbridge
26 chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
27 device pci 11.0 on end # SATA
28 device pci 12.0 on end # USB
29 device pci 12.1 on end # USB
30 device pci 12.2 on end # USB
31 device pci 13.0 on end # USB
32 device pci 13.1 on end # USB
33 device pci 13.2 on end # USB
34 device pci 14.0 on end # SM
35 device pci 14.1 on end # IDE 0x439c
36 device pci 14.2 on end # HDA 0x4383
37 device pci 14.3 on end # LPC 0x439d
38 device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
39 device pci 14.5 off end # USB 2
40 device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
41 device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector
42 device pci 16.0 off end # OHCI USB3
43 device pci 16.2 off end # EHCI USB3
44 register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
45 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
46 end #southbridge/amd/cimx/sb800
47 device pci 18.0 on end
48 device pci 18.1 on end
49 device pci 18.2 on end
50 device pci 18.3 on end
51 device pci 18.4 on end
52 device pci 18.5 on end
53 device pci 18.6 on end
54 device pci 18.7 on end
55 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
56 end #domain
57 end #northbridge/amd/agesa/family14/root_complex