src/mainboard/biostar/a68n_5200/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* This file is part of the coreboot project. */
   3
   4 /* DefinitionBlock Statement */
   5 #include <acpi/acpi.h>
   6 DefinitionBlock (
   7         "DSDT.AML",     /* Output filename */
   8         "DSDT",         /* Signature */
   9         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  10         OEM_ID,
  11         ACPI_TABLE_CREATOR,
  12         0x00010001      /* OEM Revision */
  13         )
  14 {       /* Start of ASL file */
  15         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  16
  17         /* Globals for the platform */
  18         #include "acpi/mainboard.asl"
  19
  20         /* Describe the USB Overcurrent pins */
  21         #include "acpi/usb_oc.asl"
  22
  23         /* PCI IRQ mapping for the Southbridge */
  24         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  25
  26         /* Describe the processor tree (\_SB) */
  27         #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
  28
  29         /* Contains the supported sleep states for this chipset */
  30         #include <southbridge/amd/common/acpi/sleepstates.asl>
  31
  32         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  33         #include "acpi/sleep.asl"
  34
  35         /* System Bus */
  36         Scope(\_SB) { /* Start \_SB scope */
  37                 /* global utility methods expected within the \_SB scope */
  38                 #include <arch/x86/acpi/globutil.asl>
  39
  40                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  41                 #include "acpi/routing.asl"
  42
  43                 Device(PWRB) {
  44                         Name(_HID, EISAID("PNP0C0C"))
  45                         Name(_UID, 0xAA)
  46                         Name(_PRW, Package () {3, 0x04})
  47                         Name(_STA, 0x0B)
  48                 }
  49
  50                 Device(PCI0) {
  51                         /* Describe the AMD Northbridge */
  52                         #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
  53
  54                         /* Describe the AMD Fusion Controller Hub Southbridge */
  55                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  56                 }
  57
  58                 /* Describe PCI INT[A-H] for the Southbridge */
  59                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  60
  61         } /* End \_SB scope */
  62
  63         /* Describe SMBUS for the Southbridge */
  64         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  65
  66         /* Define the General Purpose Events for the platform */
  67         #include "acpi/gpe.asl"
  68
  69         /* Define the Thermal zones and methods for the platform */
  70         #include "acpi/thermal.asl"
  71
  72         /* Define the System Indicators for the platform */
  73         #include "acpi/si.asl"
  74 }
  75 /* End of ASL file */