src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / bap / ode_e20XX / Kconfig
blob8fe8bf7c8fad4100abe95caccbf96de7e96b482c
2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 if BOARD_ODE_E20XX
9 config BOARD_SPECIFIC_OPTIONS
10         def_bool y
11         select CPU_AMD_AGESA_FAMILY16_KB
12         select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
13         select SOUTHBRIDGE_AMD_AGESA_YANGTZE
14         select DEFAULT_POST_ON_LPC
15         select HAVE_OPTION_TABLE
16         select HAVE_PIRQ_TABLE
17         select HAVE_MP_TABLE
18         select HAVE_ACPI_TABLES
19         select BOARD_ROMSIZE_KB_4096
20         select GFXUMA
21         select SUPERIO_FINTEK_F81866D
23 config MAINBOARD_DIR
24         string
25         default "bap/ode_e20XX"
27 config MAINBOARD_PART_NUMBER
28         string
29         default "ODE_E20XX"
31 config HW_MEM_HOLE_SIZEK
32         hex
33         default 0x200000
35 config MAX_CPUS
36         int
37         default 4
39 config IRQ_SLOT_COUNT
40         int
41         default 11
43 config ONBOARD_VGA_IS_PRIMARY
44         bool
45         default y
47 config HUDSON_LEGACY_FREE
48         bool
49         default y
51 choice
52         prompt "Select DDR3 clock"
53         default BAP_E20_DDR3_1066
54         help
55           Select your preferred DDR3 clock setting.
57           Note: This option changes the total power consumption.
59           If unsure, use DDR3-1066.
61 config BAP_E20_DDR3_800
62         bool "Select DDR3-800"
64 config BAP_E20_DDR3_1066
65         bool "Select DDR3-1066"
67 endchoice
69 config DIMM_SPD_SIZE
70         int
71         default 128
73 endif # BOARD_ODE_E20XX