2 ## This file is part of the coreboot project.
5 ## SPDX-License-Identifier: GPL-2.0-only
7 # -----------------------------------------------------------------
10 # -----------------------------------------------------------------
12 # -----------------------------------------------------------------
14 # -----------------------------------------------------------------
16 #96 4 r 0 status_c_rsvd
21 # -----------------------------------------------------------------
23 #104 7 r 0 status_d_rsvd
24 #111 1 r 0 valid_cmos_ram
25 # -----------------------------------------------------------------
26 # Diagnostic Status Register
29 # -----------------------------------------------------------------
30 0 120 r 0 reserved_memory
33 # -----------------------------------------------------------------
34 # RTC_BOOT_BYTE (coreboot hardcoded)
36 388 4 h 0 reboot_counter
38 # -----------------------------------------------------------------
39 # coreboot config options: console
43 #400 8 r 0 reserved for century byte
45 # -----------------------------------------------------------------
46 # coreboot config options: southbridge
48 # Non Maskable Interrupt(NMI) support, which is an interrupt that may
49 # occur on a RAM or unrecoverable error.
52 409 2 e 5 power_on_after_fail
55 # -----------------------------------------------------------------
56 # coreboot config options: northbridge
59 # Quantity of shared video memory the IGP can use
61 416 5 e 7 gfx_uma_size
63 # -----------------------------------------------------------------
64 # coreboot config options: usb3
67 # Controls how the motherboard's USB3 ports act at boot time
71 # Load (or not) pre-OS xHCI USB3 BIOS driver
76 # Streams can provide more speed (as they can use 64Kb packets),
77 # but they might cause incompatibilities with some devices.
79 424 1 e 1 usb3_streams
81 # -----------------------------------------------------------------
82 # Sandy/Ivy Bridge MRC Scrambler Seed values
83 # note: MUST NOT be covered by checksum!
84 464 32 r 0 mrc_scrambler_seed
85 496 32 r 0 mrc_scrambler_seed_s3
86 528 16 r 0 mrc_scrambler_seed_chk
88 # -----------------------------------------------------------------
89 # coreboot config options: check sums
92 # -----------------------------------------------------------------
116 # power_on_after_fail
125 # gfx_uma_size (Intel IGP Video RAM size)
159 # Disable = Use the port always as USB 2.0 for compatibility
160 # Enable = Use the port always as USB 3.0 for speed
161 # Auto = Initialize the port as USB 2.0, until the OS loads
162 # xHCI USB 3.0 driver
163 # SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
164 # and the computer is reset, keep the USB 3.0 mode.
171 # -----------------------------------------------------------------
172 # <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
173 # <bit where to start storing checksum[must be 16bits-aligned]>