src/mainboard/asus/p5qc/cmos.layout

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## SPDX-License-Identifier: GPL-2.0-only
   6
   7 # -----------------------------------------------------------------
   8 entries
   9
  10 # -----------------------------------------------------------------
  11 # Status Register A
  12 # -----------------------------------------------------------------
  13 # Status Register B
  14 # -----------------------------------------------------------------
  15 # Status Register C
  16 #96           4       r       0        status_c_rsvd
  17 #100          1       r       0        uf_flag
  18 #101          1       r       0        af_flag
  19 #102          1       r       0        pf_flag
  20 #103          1       r       0        irqf_flag
  21 # -----------------------------------------------------------------
  22 # Status Register D
  23 #104          7       r       0        status_d_rsvd
  24 #111          1       r       0        valid_cmos_ram
  25 # -----------------------------------------------------------------
  26 # Diagnostic Status Register
  27 #112          8       r       0        diag_rsvd1
  28
  29 # -----------------------------------------------------------------
  30 0          120       r       0        reserved_memory
  31 #120        264       r       0        unused
  32
  33 # -----------------------------------------------------------------
  34 # RTC_BOOT_BYTE (coreboot hardcoded)
  35 384          1       e       4        boot_option
  36 388          4       h       0        reboot_counter
  37 #390          5       r       0        unused?
  38
  39 # -----------------------------------------------------------------
  40 # coreboot config options: console
  41 395          4       e       6        debug_level
  42
  43 # coreboot config options: southbridge
  44 408         1       e       10        sata_mode
  45 409          2       e       7        power_on_after_fail
  46 411          1       e       1        nmi
  47
  48 # coreboot config options: cpu
  49 #424        8       r       0        unused
  50
  51 # coreboot config options: northbridge
  52 #432        554       r       0        unused
  53
  54 # coreboot config options: check sums
  55 984         16       h       0        check_sum
  56
  57 1024        144       r       0        recv_enable_results
  58 # -----------------------------------------------------------------
  59
  60 enumerations
  61
  62 #ID value   text
  63 1     0     Disable
  64 1     1     Enable
  65 2     0     Enable
  66 2     1     Disable
  67 4     0     Fallback
  68 4     1     Normal
  69 6     0     Emergency
  70 6     1     Alert
  71 6     2     Critical
  72 6     3     Error
  73 6     4     Warning
  74 6     5     Notice
  75 6     6     Info
  76 6     7     Debug
  77 6     8     Spew
  78 7     0     Disable
  79 7     1     Enable
  80 7     2     Keep
  81 10    0     AHCI
  82 10    1     Compatible
  83
  84 # -----------------------------------------------------------------
  85 checksums
  86
  87 checksum 392 983 984