src/: Replace GPL boilerplate with SPDX headers
[coreboot.git] / src / mainboard / apple / macbook21 / cmos.layout
blob1b433b32d145cb27fdc15c7071edecd1936f7295
2 # This file is part of the coreboot project.
5 # SPDX-License-Identifier: GPL-2.0-only
7 # -----------------------------------------------------------------
8 entries
10 # -----------------------------------------------------------------
11 # Status Register A
12 # -----------------------------------------------------------------
13 # Status Register B
14 # -----------------------------------------------------------------
15 # Status Register C
16 #96           4       r       0        status_c_rsvd
17 #100          1       r       0        uf_flag
18 #101          1       r       0        af_flag
19 #102          1       r       0        pf_flag
20 #103          1       r       0        irqf_flag
21 # -----------------------------------------------------------------
22 # Status Register D
23 #104          7       r       0        status_d_rsvd
24 #111          1       r       0        valid_cmos_ram
25 # -----------------------------------------------------------------
26 # Diagnostic Status Register
27 #112          8       r       0        diag_rsvd1
29 # -----------------------------------------------------------------
30 0          120       r       0        reserved_memory
31 #120        264       r       0        unused
33 # -----------------------------------------------------------------
34 # RTC_BOOT_BYTE (coreboot hardcoded)
35 384          1       e       4        boot_option
36 388          4       h       0        reboot_counter
37 #390          2       r       0        unused?
39 # -----------------------------------------------------------------
40 # coreboot config options: console
41 #392          3       r       0        unused
42 395          4       e       6        debug_level
43 #399          1       r       0        unused
45 # coreboot config options: cpu
46 #401          7       r       0        unused
48 # coreboot config options: southbridge
49 408          1       e       1        nmi
50 #409          2       e       7        power_on_after_fail
52 # coreboot config options: northbridge
53 411         3       e       11       gfx_uma_size
55 # coreboot config options: bootloader
56 416        512       s       0        boot_devices
57 928          8       h       0        boot_default
58 936          1       e       8        cmos_defaults_loaded
59 937          1       e       1        lpt
60 #938         46       r       0        unused
62 # coreboot config options: check sums
63 984         16       h       0        check_sum
64 #1000        24       r       0        amd_reserved
66 # RAM initialization internal data
67 1024         8       r       0        C0WL0REOST
68 1032         8       r       0        C1WL0REOST
69 1040         8       r       0        RCVENMT
70 1048         4       r       0        C0DRT1
71 1052         4       r       0        C1DRT1
73 # -----------------------------------------------------------------
75 enumerations
77 #ID value   text
78 1     0     Disable
79 1     1     Enable
80 2     0     Enable
81 2     1     Disable
82 4     0     Fallback
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84 6     0     Emergency
85 6     1     Alert
86 6     2     Critical
87 6     3     Error
88 6     4     Warning
89 6     5     Notice
90 6     6     Info
91 6     7     Debug
92 6     8     Spew
93 7     0     Disable
94 7     1     Enable
95 7     2     Keep
96 8     0     No
97 8     1     Yes
98 9     0     Secondary
99 9     1     Primary
100 11    0     1M
101 11    1     4M
102 11    2     8M
103 11    3     16M
104 11    4     32M
105 11    5     48M
106 11    6     64M
108 # -----------------------------------------------------------------
109 checksums
111 checksum 392 983 984