2 ## This file is part of the coreboot project.
4 ## SPDX-License-Identifier: GPL-2.0-only
10 helper functions for intel DDI operations
24 config INTEL_GMA_BCLV_OFFSET
28 config INTEL_GMA_BCLV_WIDTH
32 config INTEL_GMA_BCLM_OFFSET
36 config INTEL_GMA_BCLM_WIDTH
40 config INTEL_GMA_SSC_ALTERNATE_REF
44 Set when the SSC reference clock for LVDS runs at a different fre-
45 quency than the general display reference clock.
47 To be set by northbridge or mainboard Kconfig. For most platforms,
48 there is no choice, i.e. for i945 and gm45 the SSC reference always
49 differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
50 DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's
51 the same frequency for SSC/non-SSC (120MHz). The only, currently
52 supported platform with a choice seems to be Pineview, where the
53 alternative is 100MHz vs. the default 96MHz.
55 config INTEL_GMA_SWSMISCI
59 Select this option for Atom-based platforms which use the SWSMISCI
60 register (0xe0) rather than the SWSCI register (0xe8).
62 config INTEL_GMA_LIBGFXINIT_EDID
65 config GFX_GMA_ANALOG_I2C_HDMI_B
68 config GFX_GMA_ANALOG_I2C_HDMI_C
71 config GFX_GMA_ANALOG_I2C_HDMI_D
76 depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
77 || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \
78 || NORTHBRIDGE_INTEL_HASWELL \
79 || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \
80 || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \
81 || SOC_INTEL_WHISKEYLAKE
82 depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID
83 select RAMSTAGE_LIBHWBASE
85 config GFX_GMA_PANEL_1_ON_EDP
87 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT
88 default n if GFX_GMA_PANEL_1_ON_LVDS
91 config GFX_GMA_PANEL_1_ON_LVDS
93 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT
94 default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE
99 config GFX_GMA_DYN_CPU
102 Activates runtime CPU detection in libgfxinit.
104 config GFX_GMA_GENERATION
106 default "Broxton" if SOC_INTEL_APOLLOLAKE
107 default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \
108 SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
109 default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
110 default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE
111 default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
113 config GFX_GMA_PANEL_1_PORT
115 default "eDP" if GFX_GMA_PANEL_1_ON_EDP
118 config GFX_GMA_PANEL_2_PORT
122 config GFX_GMA_ANALOG_I2C_PORT
124 default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B
125 default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C
126 default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D
129 Boards with a DVI-I connector share the I2C pins for both analog and
130 digital displays. In that case, the EDID for a VGA display has to be
131 read over the I2C interface of the coupled digital port.