2 # This file is part of the coreboot project.
4 # SPDX-License-Identifier: GPL-2.0-only
8 default y if CPU_AMD_PI_00630F01
9 default y if CPU_AMD_PI_00730F01
10 default y if CPU_AMD_PI_00660F01
12 select ARCH_BOOTBLOCK_X86_32
13 select ARCH_VERSTAGE_X86_32
14 select ARCH_ROMSTAGE_X86_32
15 select ARCH_RAMSTAGE_X86_32
17 select TSC_SYNC_LFENCE
19 select LAPIC_MONOTONIC_TIMER
20 select SPI_FLASH if HAVE_ACPI_RESUME
22 select NO_FIXED_XIP_ROM_SIZE
27 config UDELAY_LAPIC_FIXED_FSB
31 # TODO: Sync these with definitions in PI vendorcode.
32 # DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
33 # DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
35 config DCACHE_RAM_BASE
39 config DCACHE_RAM_SIZE
43 config DCACHE_BSP_STACK_SIZE
47 config C_ENV_BOOTBLOCK_SIZE
53 source "src/cpu/amd/pi/00630F01/Kconfig"
54 source "src/cpu/amd/pi/00730F01/Kconfig"
55 source "src/cpu/amd/pi/00660F01/Kconfig"