src/mainboard/google/zoombini/variants/meowth/devicetree.cb

   1 chip soc/intel/cannonlake
   2
   3         # Deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "1"
   7         register "deep_s5_enable_dc" = "1"
   8
   9         # Debug Option, set to DBC over USB 3.0 port only
  10         register "DebugConsent" = "DebugConsent_USB3_DBC"
  11
  12         # GPE configuration
  13         # Note that GPE events called out in ASL code rely on this
  14         # route. i.e. If this route changes then the affected GPE
  15         # offset bits also need to be changed.
  16         register "gpe0_dw0" = "PMC_GPP_A"
  17         register "gpe0_dw1" = "PMC_GPP_B"
  18         register "gpe0_dw2" = "PMC_GPP_C"
  19
  20         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  21         register "gen1_dec" = "0x00fc0801"
  22         register "gen2_dec" = "0x000c0201"
  23         # EC memory map range is 0x900-0x9ff
  24         register "gen3_dec" = "0x00fc0901"
  25
  26         device cpu_cluster 0 on
  27                 device lapic 0 on end
  28         end
  29
  30         # FSP configuration
  31         register "SaGv" = "3"
  32         register "FspSkipMpInit" = "1"
  33         register "SmbusEnable" = "1"
  34         register "ScsEmmcEnabled" = "1"
  35         register "ScsEmmcHs400Enabled" = "1"
  36         register "ScsSdCardEnabled" = "1"
  37
  38         # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
  39         # communication before memory is up.
  40         register "gspi[0]" = "{
  41                 .speed_mhz = 1,
  42                 .early_init = 1,
  43         }"
  44
  45         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
  46         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"
  47         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  48         register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  49         register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  50         register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  51         register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  52         register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  53         register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  54         register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  55
  56         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
  57         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
  58
  59         # Touchscreen Digitizer
  60         register "i2c[0]" = "{
  61                 .speed = I2C_SPEED_FAST_PLUS,
  62                 .rise_time_ns = 98,
  63                 .fall_time_ns = 38,
  64         }"
  65
  66         register "PchHdaDspEnable" = "1"
  67         register "PchHdaAudioLinkSsp0" = "1"
  68         register "PchHdaAudioLinkSsp1" = "1"
  69
  70         # Enable cpufreq
  71         register "speed_shift_enable" = "1"
  72
  73         # Enable Root port 8 (PCIe port 9) for NVMe
  74         register "PcieRpEnable[8]" = "1"
  75         register "PcieClkSrcUsage[3]" = "8"
  76         register "PcieClkSrcClkReq[3]" = "3"
  77
  78         device domain 0 on
  79                 device pci 00.0 on  end # Host Bridge
  80                 device pci 02.0 on  end # Integrated Graphics Device
  81                 device pci 04.0 on  end # SA Thermal device
  82                 device pci 12.0 on  end # Thermal Subsystem
  83                 device pci 12.5 off end # UFS SCS
  84                 device pci 12.6 off end # GSPI #2
  85                 device pci 14.0 on  end # USB xHCI
  86                 device pci 14.1 off end # USB xDCI (OTG)
  87                 device pci 14.5 off end # SDCard
  88                 device pci 15.0 on
  89                         chip drivers/i2c/hid
  90                                 register "generic.hid" = ""WCOM50C1""
  91                                 register "generic.desc" = ""WCOM Digitizer""
  92                                 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C14_IRQ)"
  93                                 register "generic.speed" = "I2C_SPEED_FAST_PLUS"
  94                                 register "hid_desc_reg_offset" = "0x1"
  95                                 device i2c 0a on end
  96                         end
  97                 end # I2C #0
  98                 device pci 15.1 on
  99                         chip drivers/i2c/generic
 100                                 register "hid" = ""SX9310""
 101                                 register "name" = ""SEMTECH SX9310""
 102                                 register "desc" = ""Left SAR Proximity Sensor""
 103                                 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)"
 104                                 register "speed" = "I2C_SPEED_FAST_PLUS"
 105                                 register "uid" = "1"
 106                                 device i2c 28 on end
 107                         end
 108                 end # I2C #1
 109                 device pci 15.2 on end # I2C #2
 110                 device pci 15.3 on
 111                         chip drivers/i2c/max98373
 112                                 register "vmon_slot_no" = "4"
 113                                 register "imon_slot_no" = "5"
 114                                 register "uid" = "0"
 115                                 register "desc" = ""RIGHT SPEAKER AMP""
 116                                 register "name" = ""MAXR""
 117                                 device i2c 31 on end
 118                         end
 119                         chip drivers/i2c/max98373
 120                                 register "vmon_slot_no" = "6"
 121                                 register "imon_slot_no" = "7"
 122                                 register "uid" = "1"
 123                                 register "desc" = ""LEFT SPEAKER AMP""
 124                                 register "name" = ""MAXL""
 125                                 device i2c 32 on end
 126                         end
 127                 end # I2C #3
 128                 device pci 16.0 on  end # Management Engine Interface 1
 129                 device pci 16.1 off end # Management Engine Interface 2
 130                 device pci 16.2 off end # Management Engine IDE-R
 131                 device pci 16.3 off end # Management Engine KT Redirection
 132                 device pci 16.4 off end # Management Engine Interface 3
 133                 device pci 16.5 off end # Management Engine Interface 4
 134                 device pci 17.0 off end # SATA
 135                 device pci 19.0 on  end # I2C #4
 136                 device pci 19.1 on
 137                         chip drivers/i2c/generic
 138                                 register "hid" = ""SX9310""
 139                                 register "name" = ""SEMTECH SX9310""
 140                                 register "desc" = ""Right SAR Proximity Sensor""
 141                                 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)"
 142                                 register "speed" = "I2C_SPEED_FAST_PLUS"
 143                                 register "uid" = "0"
 144                                 device i2c 28 on end
 145                         end
 146                 end # I2C #5
 147                 device pci 19.2 on  end # UART #2
 148                 device pci 1a.0 on  end # eMMC
 149                 device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
 150                 device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
 151                 device pci 1c.5 off end # PCI Express Port 6
 152                 device pci 1c.6 off end # PCI Express Port 7
 153                 device pci 1c.7 off end # PCI Express Port 8
 154                 device pci 1d.0 on end # PCI Express Port 9
 155                 device pci 1d.1 off end # PCI Express Port 10
 156                 device pci 1d.2 off end # PCI Express Port 11
 157                 device pci 1d.3 off end # PCI Express Port 12
 158                 device pci 1d.4 off end # PCI Express Port 13
 159                 device pci 1d.5 off end # PCI Express Port 14
 160                 device pci 1d.6 off end # PCI Express Port 15
 161                 device pci 1d.7 off end # PCI Express Port 16
 162                 device pci 1e.0 on  end # UART #0
 163                 device pci 1e.1 off end # UART #1
 164                 device pci 1e.2 on
 165                         chip drivers/spi/acpi
 166                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 167                                 register "compat_string" = ""google,cr50""
 168                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
 169                                 device spi 0 on end
 170                         end
 171                 end # GSPI #0
 172                 device pci 1e.3 on
 173                         chip drivers/spi/acpi
 174                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 175                                 register "uid" = "1"
 176                                 register "compat_string" = ""google,cros-ec-spi""
 177                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
 178                                 device spi 0 on end
 179                         end
 180                 end # GSPI #1
 181                 device pci 1f.0 on
 182                         chip ec/google/chromeec
 183                                 device pnp 0c09.0 on end
 184                         end
 185                 end # LPC Interface
 186                 device pci 1f.1 on  end # P2SB
 187                 device pci 1f.2 on  end # Power Management Controller
 188                 device pci 1f.3 on  end # Intel HDA
 189                 device pci 1f.4 on  end # SMBus
 190                 device pci 1f.5 on  end # PCH SPI
 191                 device pci 1f.6 off end # GbE
 192         end
 193 end