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soc/intel/skylake: Generate ACPI DMAR table
[coreboot.git] / src / soc / intel / skylake / acpi.c
blob699d76affa37378e5737089e781a5c881974137b
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 * Copyright (C) 2015 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <arch/acpi.h>
19 #include <arch/acpigen.h>
20 #include <arch/cpu.h>
21 #include <arch/io.h>
22 #include <arch/ioapic.h>
23 #include <arch/smp/mpspec.h>
24 #include <cbmem.h>
25 #include <chip.h>
26 #include <console/console.h>
27 #include <cpu/cpu.h>
28 #include <cpu/x86/smm.h>
29 #include <cpu/x86/msr.h>
30 #include <cpu/x86/tsc.h>
31 #include <cpu/intel/turbo.h>
32 #include <ec/google/chromeec/ec.h>
33 #include <intelblocks/cpulib.h>
34 #include <intelblocks/lpc_lib.h>
35 #include <intelblocks/sgx.h>
36 #include <intelblocks/uart.h>
37 #include <intelblocks/systemagent.h>
38 #include <soc/intel/common/acpi.h>
39 #include <soc/acpi.h>
40 #include <soc/cpu.h>
41 #include <soc/iomap.h>
42 #include <soc/msr.h>
43 #include <soc/p2sb.h>
44 #include <soc/pci_devs.h>
45 #include <soc/pm.h>
46 #include <soc/ramstage.h>
47 #include <soc/systemagent.h>
48 #include <string.h>
49 #include <types.h>
50 #include <vendorcode/google/chromeos/gnvs.h>
51 #include <wrdd.h>
52
53 /*
54 * List of suported C-states in this processor.
55 */
56 enum {
57 C_STATE_C0, /* 0 */
58 C_STATE_C1, /* 1 */
59 C_STATE_C1E, /* 2 */
60 C_STATE_C3, /* 3 */
61 C_STATE_C6_SHORT_LAT, /* 4 */
62 C_STATE_C6_LONG_LAT, /* 5 */
63 C_STATE_C7_SHORT_LAT, /* 6 */
64 C_STATE_C7_LONG_LAT, /* 7 */
65 C_STATE_C7S_SHORT_LAT, /* 8 */
66 C_STATE_C7S_LONG_LAT, /* 9 */
67 C_STATE_C8, /* 10 */
68 C_STATE_C9, /* 11 */
69 C_STATE_C10, /* 12 */
70 NUM_C_STATES
71 };
72 #define MWAIT_RES(state, sub_state) \
73 { \
74 .addrl = (((state) << 4) | (sub_state)), \
75 .space_id = ACPI_ADDRESS_SPACE_FIXED, \
76 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
77 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
78 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
79 }
80
81 static acpi_cstate_t cstate_map[NUM_C_STATES] = {
82 [C_STATE_C0] = { },
83 [C_STATE_C1] = {
84 .latency = 0,
85 .power = C1_POWER,
86 .resource = MWAIT_RES(0, 0),
87 },
88 [C_STATE_C1E] = {
89 .latency = 0,
90 .power = C1_POWER,
91 .resource = MWAIT_RES(0, 1),
92 },
93 [C_STATE_C3] = {
94 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
95 .power = C3_POWER,
96 .resource = MWAIT_RES(1, 0),
97 },
98 [C_STATE_C6_SHORT_LAT] = {
99 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
100 .power = C6_POWER,
101 .resource = MWAIT_RES(2, 0),
102 },
103 [C_STATE_C6_LONG_LAT] = {
104 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
105 .power = C6_POWER,
106 .resource = MWAIT_RES(2, 1),
107 },
108 [C_STATE_C7_SHORT_LAT] = {
109 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
110 .power = C7_POWER,
111 .resource = MWAIT_RES(3, 0),
112 },
113 [C_STATE_C7_LONG_LAT] = {
114 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
115 .power = C7_POWER,
116 .resource = MWAIT_RES(3, 1),
117 },
118 [C_STATE_C7S_SHORT_LAT] = {
119 .latency = C_STATE_LATENCY_FROM_LAT_REG(1),
120 .power = C7_POWER,
121 .resource = MWAIT_RES(3, 2),
122 },
123 [C_STATE_C7S_LONG_LAT] = {
124 .latency = C_STATE_LATENCY_FROM_LAT_REG(2),
125 .power = C7_POWER,
126 .resource = MWAIT_RES(3, 3),
127 },
128 [C_STATE_C8] = {
129 .latency = C_STATE_LATENCY_FROM_LAT_REG(3),
130 .power = C8_POWER,
131 .resource = MWAIT_RES(4, 0),
132 },
133 [C_STATE_C9] = {
134 .latency = C_STATE_LATENCY_FROM_LAT_REG(4),
135 .power = C9_POWER,
136 .resource = MWAIT_RES(5, 0),
137 },
138 [C_STATE_C10] = {
139 .latency = C_STATE_LATENCY_FROM_LAT_REG(5),
140 .power = C10_POWER,
141 .resource = MWAIT_RES(6, 0),
142 },
143 };
144
145 static int cstate_set_s0ix[] = {
146 C_STATE_C1E,
147 C_STATE_C7S_LONG_LAT,
148 C_STATE_C10
149 };
150
151 static int cstate_set_non_s0ix[] = {
152 C_STATE_C1E,
153 C_STATE_C3,
154 C_STATE_C7S_LONG_LAT,
155 };
156
157 static int get_cores_per_package(void)
158 {
159 struct cpuinfo_x86 c;
160 struct cpuid_result result;
161 int cores = 1;
162
163 get_fms(&c, cpuid_eax(1));
164 if (c.x86 != 6)
165 return 1;
166
167 result = cpuid_ext(0xb, 1);
168 cores = result.ebx & 0xff;
169
170 return cores;
171 }
172
173 static void acpi_create_gnvs(global_nvs_t *gnvs)
174 {
175 const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
176 const struct soc_intel_skylake_config *config = dev->chip_info;
177
178 /* Set unknown wake source */
179 gnvs->pm1i = -1;
180
181 /* CPU core count */
182 gnvs->pcnt = dev_count_cpu();
183
184 #if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
185 /* Update the mem console pointer. */
186 gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
187 #endif
188
189 #if IS_ENABLED(CONFIG_CHROMEOS)
190 /* Initialize Verified Boot data */
191 chromeos_init_vboot(&(gnvs->chromeos));
192 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
193 gnvs->chromeos.vbt2 = google_ec_running_ro() ?
194 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
195 #endif
196 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
197 #endif
198
199 /* Enable DPTF based on mainboard configuration */
200 gnvs->dpte = config->dptf_enable;
201
202 /* Fill in the Wifi Region id */
203 gnvs->cid1 = wifi_regulatory_domain();
204
205 /* Set USB2/USB3 wake enable bitmaps. */
206 gnvs->u2we = config->usb2_wake_enable_bitmap;
207 gnvs->u3we = config->usb3_wake_enable_bitmap;
208
209 if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
210 sgx_fill_gnvs(gnvs);
211 }
212
213 unsigned long acpi_fill_mcfg(unsigned long current)
214 {
215 current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
216 CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
217 (CONFIG_SA_PCIEX_LENGTH >> 20) - 1);
218 return current;
219 }
220
221 unsigned long acpi_fill_madt(unsigned long current)
222 {
223 /* Local APICs */
224 current = acpi_create_madt_lapics(current);
225
226 /* IOAPIC */
227 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
228 2, IO_APIC_ADDR, 0);
229
230 return acpi_madt_irq_overrides(current);
231 }
232
233 void acpi_fill_fadt(acpi_fadt_t *fadt)
234 {
235 const uint16_t pmbase = ACPI_BASE_ADDRESS;
236
237 /* Use ACPI 3.0 revision */
238 fadt->header.revision = ACPI_FADT_REV_ACPI_3_0;
239
240 fadt->sci_int = acpi_sci_irq();
241 fadt->smi_cmd = APM_CNT;
242 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
243 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
244 fadt->s4bios_req = 0x0;
245 fadt->pstate_cnt = 0;
246
247 fadt->pm1a_evt_blk = pmbase + PM1_STS;
248 fadt->pm1b_evt_blk = 0x0;
249 fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
250 fadt->pm1b_cnt_blk = 0x0;
251 fadt->pm2_cnt_blk = pmbase + PM2_CNT;
252 fadt->pm_tmr_blk = pmbase + PM1_TMR;
253 fadt->gpe0_blk = pmbase + GPE0_STS(0);
254 fadt->gpe1_blk = 0;
255
256 fadt->pm1_evt_len = 4;
257 fadt->pm1_cnt_len = 2;
258 fadt->pm2_cnt_len = 1;
259 fadt->pm_tmr_len = 4;
260 /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
261 fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
262 fadt->gpe1_blk_len = 0;
263 fadt->gpe1_base = 0;
264 fadt->cst_cnt = 0;
265 fadt->p_lvl2_lat = 1;
266 fadt->p_lvl3_lat = 87;
267 fadt->flush_size = 1024;
268 fadt->flush_stride = 16;
269 fadt->duty_offset = 1;
270 fadt->duty_width = 0;
271 fadt->day_alrm = 0xd;
272 fadt->mon_alrm = 0x00;
273 fadt->century = 0x00;
274 fadt->iapc_boot_arch = 0;
275 if (!IS_ENABLED(CONFIG_NO_FADT_8042))
276 fadt->iapc_boot_arch |= ACPI_FADT_8042;
277
278 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
279 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
280 ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
281 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
282
283 fadt->reset_reg.space_id = 1;
284 fadt->reset_reg.bit_width = 8;
285 fadt->reset_reg.bit_offset = 0;
286 fadt->reset_reg.resv = 0;
287 fadt->reset_reg.addrl = 0xcf9;
288 fadt->reset_reg.addrh = 0;
289 fadt->reset_value = 6;
290
291 fadt->x_pm1a_evt_blk.space_id = 1;
292 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
293 fadt->x_pm1a_evt_blk.bit_offset = 0;
294 fadt->x_pm1a_evt_blk.resv = 0;
295 fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
296 fadt->x_pm1a_evt_blk.addrh = 0x0;
297
298 fadt->x_pm1b_evt_blk.space_id = 1;
299 fadt->x_pm1b_evt_blk.bit_width = 0;
300 fadt->x_pm1b_evt_blk.bit_offset = 0;
301 fadt->x_pm1b_evt_blk.resv = 0;
302 fadt->x_pm1b_evt_blk.addrl = 0x0;
303 fadt->x_pm1b_evt_blk.addrh = 0x0;
304
305 fadt->x_pm1a_cnt_blk.space_id = 1;
306 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
307 fadt->x_pm1a_cnt_blk.bit_offset = 0;
308 fadt->x_pm1a_cnt_blk.resv = 0;
309 fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
310 fadt->x_pm1a_cnt_blk.addrh = 0x0;
311
312 fadt->x_pm1b_cnt_blk.space_id = 1;
313 fadt->x_pm1b_cnt_blk.bit_width = 0;
314 fadt->x_pm1b_cnt_blk.bit_offset = 0;
315 fadt->x_pm1b_cnt_blk.resv = 0;
316 fadt->x_pm1b_cnt_blk.addrl = 0x0;
317 fadt->x_pm1b_cnt_blk.addrh = 0x0;
318
319 fadt->x_pm2_cnt_blk.space_id = 1;
320 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
321 fadt->x_pm2_cnt_blk.bit_offset = 0;
322 fadt->x_pm2_cnt_blk.resv = 0;
323 fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
324 fadt->x_pm2_cnt_blk.addrh = 0x0;
325
326 fadt->x_pm_tmr_blk.space_id = 1;
327 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
328 fadt->x_pm_tmr_blk.bit_offset = 0;
329 fadt->x_pm_tmr_blk.resv = 0;
330 fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
331 fadt->x_pm_tmr_blk.addrh = 0x0;
332
333 fadt->x_gpe0_blk.space_id = 0;
334 fadt->x_gpe0_blk.bit_width = 0;
335 fadt->x_gpe0_blk.bit_offset = 0;
336 fadt->x_gpe0_blk.resv = 0;
337 fadt->x_gpe0_blk.addrl = 0;
338 fadt->x_gpe0_blk.addrh = 0;
339
340 fadt->x_gpe1_blk.space_id = 1;
341 fadt->x_gpe1_blk.bit_width = 0;
342 fadt->x_gpe1_blk.bit_offset = 0;
343 fadt->x_gpe1_blk.resv = 0;
344 fadt->x_gpe1_blk.addrl = 0x0;
345 fadt->x_gpe1_blk.addrh = 0x0;
346 }
347
348 static void generate_c_state_entries(int s0ix_enable, int max_cstate)
349 {
350
351 acpi_cstate_t map[max_cstate];
352 int *set;
353 int i;
354
355 if (s0ix_enable)
356 set = cstate_set_s0ix;
357 else
358 set = cstate_set_non_s0ix;
359
360 for (i = 0; i < max_cstate; i++) {
361 memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
362 map[i].ctype = i + 1;
363 }
364
365 /* Generate C-state tables */
366 acpigen_write_CST_package(map, ARRAY_SIZE(map));
367 }
368
369 static int calculate_power(int tdp, int p1_ratio, int ratio)
370 {
371 u32 m;
372 u32 power;
373
374 /*
375 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
376 *
377 * Power = (ratio / p1_ratio) * m * tdp
378 */
379
380 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
381 m = (m * m) / 1000;
382
383 power = ((ratio * 100000 / p1_ratio) / 100);
384 power *= (m / 100) * (tdp / 1000);
385 power /= 1000;
386
387 return (int)power;
388 }
389
390 static void generate_p_state_entries(int core, int cores_per_package)
391 {
392 int ratio_min, ratio_max, ratio_turbo, ratio_step;
393 int coord_type, power_max, power_unit, num_entries;
394 int ratio, power, clock, clock_max;
395 msr_t msr;
396
397 /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
398 msr = rdmsr(MSR_MISC_PWR_MGMT);
399 if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
400 coord_type = SW_ANY;
401 else
402 coord_type = HW_ALL;
403
404 /* Get bus ratio limits and calculate clock speeds */
405 msr = rdmsr(MSR_PLATFORM_INFO);
406 ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
407
408 /* Determine if this CPU has configurable TDP */
409 if (cpu_config_tdp_levels()) {
410 /* Set max ratio to nominal TDP ratio */
411 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
412 ratio_max = msr.lo & 0xff;
413 } else {
414 /* Max Non-Turbo Ratio */
415 ratio_max = (msr.lo >> 8) & 0xff;
416 }
417 clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
418
419 /* Calculate CPU TDP in mW */
420 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
421 power_unit = 2 << ((msr.lo & 0xf) - 1);
422 msr = rdmsr(MSR_PKG_POWER_SKU);
423 power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
424
425 /* Write _PCT indicating use of FFixedHW */
426 acpigen_write_empty_PCT();
427
428 /* Write _PPC with no limit on supported P-state */
429 acpigen_write_PPC_NVS();
430
431 /* Write PSD indicating configured coordination type */
432 acpigen_write_PSD_package(core, 1, coord_type);
433
434 /* Add P-state entries in _PSS table */
435 acpigen_write_name("_PSS");
436
437 /* Determine ratio points */
438 ratio_step = PSS_RATIO_STEP;
439 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
440 if (num_entries > PSS_MAX_ENTRIES) {
441 ratio_step += 1;
442 num_entries = ((ratio_max - ratio_min) / ratio_step) + 1;
443 }
444
445 /* P[T] is Turbo state if enabled */
446 if (get_turbo_state() == TURBO_ENABLED) {
447 /* _PSS package count including Turbo */
448 acpigen_write_package(num_entries + 2);
449
450 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
451 ratio_turbo = msr.lo & 0xff;
452
453 /* Add entry for Turbo ratio */
454 acpigen_write_PSS_package(
455 clock_max + 1, /* MHz */
456 power_max, /* mW */
457 PSS_LATENCY_TRANSITION, /* lat1 */
458 PSS_LATENCY_BUSMASTER, /* lat2 */
459 ratio_turbo << 8, /* control */
460 ratio_turbo << 8); /* status */
461 } else {
462 /* _PSS package count without Turbo */
463 acpigen_write_package(num_entries + 1);
464 }
465
466 /* First regular entry is max non-turbo ratio */
467 acpigen_write_PSS_package(
468 clock_max, /* MHz */
469 power_max, /* mW */
470 PSS_LATENCY_TRANSITION, /* lat1 */
471 PSS_LATENCY_BUSMASTER, /* lat2 */
472 ratio_max << 8, /* control */
473 ratio_max << 8); /* status */
474
475 /* Generate the remaining entries */
476 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
477 ratio >= ratio_min; ratio -= ratio_step) {
478
479 /* Calculate power at this ratio */
480 power = calculate_power(power_max, ratio_max, ratio);
481 clock = ratio * CONFIG_CPU_BCLK_MHZ;
482
483 acpigen_write_PSS_package(
484 clock, /* MHz */
485 power, /* mW */
486 PSS_LATENCY_TRANSITION, /* lat1 */
487 PSS_LATENCY_BUSMASTER, /* lat2 */
488 ratio << 8, /* control */
489 ratio << 8); /* status */
490 }
491
492 /* Fix package length */
493 acpigen_pop_len();
494 }
495
496 void generate_cpu_entries(device_t device)
497 {
498 int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
499 int totalcores = dev_count_cpu();
500 int cores_per_package = get_cores_per_package();
501 int numcpus = totalcores/cores_per_package;
502 device_t dev = SA_DEV_ROOT;
503 config_t *config = dev->chip_info;
504 int is_s0ix_enable = config->s0ix_enable;
505 int max_c_state;
506
507 if (is_s0ix_enable)
508 max_c_state = ARRAY_SIZE(cstate_set_s0ix);
509 else
510 max_c_state = ARRAY_SIZE(cstate_set_non_s0ix);
511
512 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
513 numcpus, cores_per_package);
514
515 for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
516 for (core_id = 0; core_id < cores_per_package; core_id++) {
517 if (core_id > 0) {
518 pcontrol_blk = 0;
519 plen = 0;
520 }
521
522 /* Generate processor \_PR.CPUx */
523 acpigen_write_processor(
524 cpu_id*cores_per_package+core_id,
525 pcontrol_blk, plen);
526 /* Generate C-state tables */
527 generate_c_state_entries(is_s0ix_enable,
528 max_c_state);
529
530 if (config->eist_enable)
531 /* Generate P-state tables */
532 generate_p_state_entries(core_id,
533 cores_per_package);
534
535 acpigen_pop_len();
536 }
537 }
538 }
539
540 static unsigned long acpi_fill_dmar(unsigned long current)
541 {
542 struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
543 const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
544 const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
545
546 /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
547 if (igfx_dev && igfx_dev->enabled && gfxvten &&
548 gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {
549 const unsigned long tmp = current;
550
551 current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
552 current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
553
554 acpi_dmar_drhd_fixup(tmp, current);
555 }
556
557 struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
558 const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
559 const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
560
561 /* General VTBAR has to be set and in 32-bit space. */
562 if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
563 const unsigned long tmp = current;
564
565 /* P2SB may already be hidden. There's no clear rule, when. */
566 const u8 p2sb_hidden =
567 pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1);
568 pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0);
569
570 const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF);
571 const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF);
572
573 pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden);
574
575 current += acpi_create_dmar_drhd(current,
576 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
577 current += acpi_create_dmar_drhd_ds_ioapic(current,
578 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf));
579 current += acpi_create_dmar_drhd_ds_msi_hpet(current,
580 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf));
581
582 acpi_dmar_drhd_fixup(tmp, current);
583 }
584
585 return current;
586 }
587
588 unsigned long northbridge_write_acpi_tables(struct device *const dev,
589 unsigned long current,
590 struct acpi_rsdp *const rsdp)
591 {
592 const struct soc_intel_skylake_config *const config = dev->chip_info;
593 acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
594
595 /* Create DMAR table only if we have VT-d capability. */
596 if ((config && config->ignore_vtd) || !soc_is_vtd_capable())
597 return current;
598
599 printk(BIOS_DEBUG, "ACPI: * DMAR\n");
600 acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
601 current += dmar->header.length;
602 current = acpi_align_current(current);
603 acpi_add_table(rsdp, dmar);
604
605 return current;
606 }
607
608 unsigned long acpi_madt_irq_overrides(unsigned long current)
609 {
610 int sci = acpi_sci_irq();
611 acpi_madt_irqoverride_t *irqovr;
612 uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
613
614 /* INT_SRC_OVR */
615 irqovr = (void *)current;
616 current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
617
618 if (sci >= 20)
619 flags |= MP_IRQ_POLARITY_LOW;
620 else
621 flags |= MP_IRQ_POLARITY_HIGH;
622
623 /* SCI */
624 irqovr = (void *)current;
625 current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags);
626
627 return current;
628 }
629
630 unsigned long southbridge_write_acpi_tables(device_t device,
631 unsigned long current,
632 struct acpi_rsdp *rsdp)
633 {
634 current = acpi_write_dbg2_pci_uart(rsdp, current,
635 pch_uart_get_debug_controller(),
636 ACPI_ACCESS_SIZE_DWORD_ACCESS);
637 current = acpi_write_hpet(device, current, rsdp);
638 return acpi_align_current(current);
639 }
640
641 void southbridge_inject_dsdt(device_t device)
642 {
643 global_nvs_t *gnvs;
644
645 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
646 if (!gnvs) {
647 gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
648 if (gnvs)
649 memset(gnvs, 0, sizeof(*gnvs));
650 }
651
652 if (gnvs) {
653 acpi_create_gnvs(gnvs);
654 acpi_mainboard_gnvs(gnvs);
655 acpi_save_gnvs((unsigned long)gnvs);
656 /* And tell SMI about it */
657 smm_setup_structures(gnvs, NULL, NULL);
658
659 /* Add it to DSDT. */
660 acpigen_write_scope("\\");
661 acpigen_write_name_dword("NVSA", (u32) gnvs);
662 acpigen_pop_len();
663 }
664 }
665
666 /* Save wake source information for calculating ACPI _SWS values */
667 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
668 {
669 const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
670 const struct soc_intel_skylake_config *config = dev->chip_info;
671 struct chipset_power_state *ps;
672 static uint32_t gpe0_sts[GPE0_REG_MAX];
673 uint32_t pm1_en;
674 uint32_t gpe0_std;
675 int i;
676 const int last_index = GPE0_REG_MAX - 1;
677
678 ps = cbmem_find(CBMEM_ID_POWER_STATE);
679 if (ps == NULL)
680 return -1;
681
682 pm1_en = ps->pm1_en;
683 gpe0_std = ps->gpe0_en[3];
684
685 /*
686 * Chipset state in the suspend well (but not RTC) is lost in Deep S3
687 * so enable Deep S3 wake events that are configured by the mainboard
688 */
689 if (ps->prev_sleep_state == ACPI_S3 &&
690 (config->deep_s3_enable_ac || config->deep_s3_enable_dc)) {
691 pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
692 if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
693 gpe0_std |= LAN_WAK_EN;
694 if (config->deep_sx_config & DSX_EN_WAKE_PIN)
695 pm1_en |= PCIEXPWAK_STS;
696 }
697
698 *pm1 = ps->pm1_sts & pm1_en;
699
700 /* Mask off GPE0 status bits that are not enabled */
701 *gpe0 = &gpe0_sts[0];
702 for (i = 0; i < last_index; i++)
703 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
704 gpe0_sts[last_index] = ps->gpe0_sts[last_index] & gpe0_std;
705
706 return GPE0_REG_MAX;
707 }
708
709 __attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
710 {
711 }
712
713 const char *soc_acpi_name(const struct device *dev)
714 {
715 if (dev->path.type == DEVICE_PATH_DOMAIN)
716 return "PCI0";
717
718 if (dev->path.type != DEVICE_PATH_PCI)
719 return NULL;
720
721 switch (dev->path.pci.devfn) {
722 case SA_DEVFN_ROOT: return "MCHC";
723 case SA_DEVFN_IGD: return "GFX0";
724 case PCH_DEVFN_ISH: return "ISHB";
725 case PCH_DEVFN_XHCI: return "XHCI";
726 case PCH_DEVFN_USBOTG: return "XDCI";
727 case PCH_DEVFN_THERMAL: return "THRM";
728 case PCH_DEVFN_CIO: return "ICIO";
729 case PCH_DEVFN_I2C0: return "I2C0";
730 case PCH_DEVFN_I2C1: return "I2C1";
731 case PCH_DEVFN_I2C2: return "I2C2";
732 case PCH_DEVFN_I2C3: return "I2C3";
733 case PCH_DEVFN_CSE: return "CSE1";
734 case PCH_DEVFN_CSE_2: return "CSE2";
735 case PCH_DEVFN_CSE_IDER: return "CSED";
736 case PCH_DEVFN_CSE_KT: return "CSKT";
737 case PCH_DEVFN_CSE_3: return "CSE3";
738 case PCH_DEVFN_SATA: return "SATA";
739 case PCH_DEVFN_UART2: return "UAR2";
740 case PCH_DEVFN_I2C4: return "I2C4";
741 case PCH_DEVFN_I2C5: return "I2C5";
742 case PCH_DEVFN_PCIE1: return "RP01";
743 case PCH_DEVFN_PCIE2: return "RP02";
744 case PCH_DEVFN_PCIE3: return "RP03";
745 case PCH_DEVFN_PCIE4: return "RP04";
746 case PCH_DEVFN_PCIE5: return "RP05";
747 case PCH_DEVFN_PCIE6: return "RP06";
748 case PCH_DEVFN_PCIE7: return "RP07";
749 case PCH_DEVFN_PCIE8: return "RP08";
750 case PCH_DEVFN_PCIE9: return "RP09";
751 case PCH_DEVFN_PCIE10: return "RP10";
752 case PCH_DEVFN_PCIE11: return "RP11";
753 case PCH_DEVFN_PCIE12: return "RP12";
754 case PCH_DEVFN_UART0: return "UAR0";
755 case PCH_DEVFN_UART1: return "UAR1";
756 case PCH_DEVFN_GSPI0: return "SPI0";
757 case PCH_DEVFN_GSPI1: return "SPI1";
758 case PCH_DEVFN_EMMC: return "EMMC";
759 case PCH_DEVFN_SDIO: return "SDIO";
760 case PCH_DEVFN_SDCARD: return "SDXC";
761 case PCH_DEVFN_LPC: return "LPCB";
762 case PCH_DEVFN_P2SB: return "P2SB";
763 case PCH_DEVFN_PMC: return "PMC_";
764 case PCH_DEVFN_HDA: return "HDAS";
765 case PCH_DEVFN_SMBUS: return "SBUS";
766 case PCH_DEVFN_SPI: return "FSPI";
767 case PCH_DEVFN_GBE: return "IGBE";
768 case PCH_DEVFN_TRACEHUB:return "THUB";
769 }
770
771 return NULL;
772 }
773
774 static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
775 {
776 /* op (gpio_num) */
777 acpigen_emit_namestring(op);
778 acpigen_write_integer(gpio_num);
779 return 0;
780 }
781
782 static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
783 {
784 /* Store (op (gpio_num), Local0) */
785 acpigen_write_store();
786 acpigen_soc_gpio_op(op, gpio_num);
787 acpigen_emit_byte(LOCAL0_OP);
788 return 0;
789 }
790
791 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
792 {
793 return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
794 }
795
796 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
797 {
798 return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
799 }
800
801 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
802 {
803 return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
804 }
805
806 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
807 {
808 return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
809 }
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