src/soc/intel/jasperlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <device/device.h>
   7 #include <device/mmio.h>
   8 #include <arch/smp/mpspec.h>
   9 #include <cbmem.h>
  10 #include <console/console.h>
  11 #include <device/pci_ops.h>
  12 #include <intelblocks/cpulib.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/acpi.h>
  15 #include <soc/cpu.h>
  16 #include <soc/iomap.h>
  17 #include <soc/nvs.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22 #include <string.h>
  23 #include <wrdd.h>
  24
  25 /*
  26  * List of supported C-states in this processor.
  27  */
  28 enum {
  29         C_STATE_C0,             /* 0 */
  30         C_STATE_C1,             /* 1 */
  31         C_STATE_C1E,            /* 2 */
  32         C_STATE_C6_SHORT_LAT,   /* 3 */
  33         C_STATE_C6_LONG_LAT,    /* 4 */
  34         C_STATE_C7_SHORT_LAT,   /* 5 */
  35         C_STATE_C7_LONG_LAT,    /* 6 */
  36         C_STATE_C7S_SHORT_LAT,  /* 7 */
  37         C_STATE_C7S_LONG_LAT,   /* 8 */
  38         C_STATE_C8,             /* 9 */
  39         C_STATE_C9,             /* 10 */
  40         C_STATE_C10,            /* 11 */
  41         NUM_C_STATES
  42 };
  43
  44 #define MWAIT_RES(state, sub_state)                             \
  45         {                                                       \
  46                 .addrl = (((state) << 4) | (sub_state)),        \
  47                 .space_id = ACPI_ADDRESS_SPACE_FIXED,           \
  48                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,        \
  49                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,        \
  50                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,     \
  51         }
  52
  53 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  54         [C_STATE_C0] = {},
  55         [C_STATE_C1] = {
  56                 .latency = C1_LATENCY,
  57                 .power = C1_POWER,
  58                 .resource = MWAIT_RES(0, 0),
  59         },
  60         [C_STATE_C1E] = {
  61                 .latency = C1_LATENCY,
  62                 .power = C1_POWER,
  63                 .resource = MWAIT_RES(0, 1),
  64         },
  65         [C_STATE_C6_SHORT_LAT] = {
  66                 .latency = C6_LATENCY,
  67                 .power = C6_POWER,
  68                 .resource = MWAIT_RES(2, 0),
  69         },
  70         [C_STATE_C6_LONG_LAT] = {
  71                 .latency = C6_LATENCY,
  72                 .power = C6_POWER,
  73                 .resource = MWAIT_RES(2, 1),
  74         },
  75         [C_STATE_C7_SHORT_LAT] = {
  76                 .latency = C7_LATENCY,
  77                 .power = C7_POWER,
  78                 .resource = MWAIT_RES(3, 0),
  79         },
  80         [C_STATE_C7_LONG_LAT] = {
  81                 .latency = C7_LATENCY,
  82                 .power = C7_POWER,
  83                 .resource = MWAIT_RES(3, 1),
  84         },
  85         [C_STATE_C7S_SHORT_LAT] = {
  86                 .latency = C7_LATENCY,
  87                 .power = C7_POWER,
  88                 .resource = MWAIT_RES(3, 2),
  89         },
  90         [C_STATE_C7S_LONG_LAT] = {
  91                 .latency = C7_LATENCY,
  92                 .power = C7_POWER,
  93                 .resource = MWAIT_RES(3, 3),
  94         },
  95         [C_STATE_C8] = {
  96                 .latency = C8_LATENCY,
  97                 .power = C8_POWER,
  98                 .resource = MWAIT_RES(4, 0),
  99         },
 100         [C_STATE_C9] = {
 101                 .latency = C9_LATENCY,
 102                 .power = C9_POWER,
 103                 .resource = MWAIT_RES(5, 0),
 104         },
 105         [C_STATE_C10] = {
 106                 .latency = C10_LATENCY,
 107                 .power = C10_POWER,
 108                 .resource = MWAIT_RES(6, 0),
 109         },
 110 };
 111
 112 static int cstate_set_non_s0ix[] = {
 113         C_STATE_C1,
 114         C_STATE_C6_LONG_LAT,
 115         C_STATE_C7S_LONG_LAT
 116 };
 117
 118 static int cstate_set_s0ix[] = {
 119         C_STATE_C1,
 120         C_STATE_C7S_LONG_LAT,
 121         C_STATE_C10
 122 };
 123
 124 acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 125 {
 126         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 127                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 128         int *set;
 129         int i;
 130
 131         config_t *config = config_of_soc();
 132
 133         int is_s0ix_enable = config->s0ix_enable;
 134
 135         if (is_s0ix_enable) {
 136                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 137                 set = cstate_set_s0ix;
 138         } else {
 139                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 140                 set = cstate_set_non_s0ix;
 141         }
 142
 143         for (i = 0; i < *entries; i++) {
 144                 memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
 145                 map[i].ctype = i + 1;
 146         }
 147         return map;
 148 }
 149
 150 void soc_power_states_generation(int core_id, int cores_per_package)
 151 {
 152         config_t *config = config_of_soc();
 153
 154         if (config->eist_enable)
 155                 /* Generate P-state tables */
 156                 generate_p_state_entries(core_id, cores_per_package);
 157 }
 158
 159 void soc_fill_fadt(acpi_fadt_t *fadt)
 160 {
 161         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 162
 163         config_t *config = config_of_soc();
 164
 165         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 166         fadt->pm_tmr_len = 4;
 167         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 168         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 169         fadt->x_pm_tmr_blk.bit_offset = 0;
 170         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
 171         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 172         fadt->x_pm_tmr_blk.addrh = 0x0;
 173
 174         if (config->s0ix_enable)
 175                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 176 }
 177
 178 uint32_t soc_read_sci_irq_select(void)
 179 {
 180         uintptr_t pmc_bar = soc_read_pmc_base();
 181         return read32((void *)pmc_bar + IRQ_REG);
 182 }
 183
 184 static unsigned long soc_fill_dmar(unsigned long current)
 185 {
 186         const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 187         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 188         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 189
 190         if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) {
 191                 unsigned long tmp = current;
 192
 193                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 194                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 195
 196                 acpi_dmar_drhd_fixup(tmp, current);
 197         }
 198
 199         const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
 200         uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 201         bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 202
 203         if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) {
 204                 unsigned long tmp = current;
 205
 206                 current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
 207                 current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
 208
 209                 acpi_dmar_drhd_fixup(tmp, current);
 210         }
 211
 212         uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 213         bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 214
 215         if (vtvc0bar && vtvc0en) {
 216                 const unsigned long tmp = current;
 217
 218                 current += acpi_create_dmar_drhd(current,
 219                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 220                 current += acpi_create_dmar_ds_ioapic(current,
 221                                 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 222                                 V_P2SB_CFG_IBDF_FUNC);
 223                 current += acpi_create_dmar_ds_msi_hpet(current,
 224                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 225                                 V_P2SB_CFG_HBDF_FUNC);
 226
 227                 acpi_dmar_drhd_fixup(tmp, current);
 228         }
 229
 230         /* TCSS Thunderbolt root ports */
 231         for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
 232                 uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
 233                 bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
 234                 if (tbtbar && tbten) {
 235                         unsigned long tmp = current;
 236
 237                         current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
 238                         current += acpi_create_dmar_ds_pci(current, 0, 7, i);
 239
 240                         acpi_dmar_drhd_fixup(tmp, current);
 241                 }
 242         }
 243
 244         /* Add RMRR entry */
 245         const unsigned long tmp = current;
 246         current += acpi_create_dmar_rmrr(current, 0,
 247                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 248         current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 249         acpi_dmar_rmrr_fixup(tmp, current);
 250
 251         return current;
 252 }
 253
 254 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 255                                    struct acpi_rsdp *rsdp)
 256 {
 257         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 258
 259         /*
 260          * Create DMAR table only if we have VT-d capability and FSP does not override its
 261          * feature.
 262          */
 263         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 264             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 265                 return current;
 266
 267         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 268         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 269         current += dmar->header.length;
 270         current = acpi_align_current(current);
 271         acpi_add_table(rsdp, dmar);
 272
 273         return current;
 274 }
 275
 276 void soc_fill_gnvs(struct global_nvs *gnvs)
 277 {
 278         config_t *config = config_of_soc();
 279
 280         /* Set unknown wake source */
 281         gnvs->pm1i = -1;
 282
 283         /* CPU core count */
 284         gnvs->pcnt = dev_count_cpu();
 285
 286         /* Enable DPTF based on mainboard configuration */
 287         gnvs->dpte = config->dptf_enable;
 288
 289         /* Fill in the Wifi Region id */
 290         gnvs->cid1 = wifi_regulatory_domain();
 291
 292         /* Set USB2/USB3 wake enable bitmaps. */
 293         gnvs->u2we = config->usb2_wake_enable_bitmap;
 294         gnvs->u3we = config->usb3_wake_enable_bitmap;
 295
 296         /* Fill in Above 4GB MMIO resource */
 297         sa_fill_gnvs(gnvs);
 298 }
 299
 300 uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
 301                             const struct chipset_power_state *ps)
 302 {
 303         /*
 304          * WAK_STS bit is set when the system is in one of the sleep states
 305          * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
 306          * this bit, the PMC will transition the system to the ON state and
 307          * can only be set by hardware and can only be cleared by writing a one
 308          * to this bit position.
 309          */
 310
 311         generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
 312         return generic_pm1_en;
 313 }
 314
 315 int soc_madt_sci_irq_polarity(int sci)
 316 {
 317         return MP_IRQ_POLARITY_HIGH;
 318 }
 319
 320 static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
 321 {
 322         /* op (gpio_num) */
 323         acpigen_emit_namestring(op);
 324         acpigen_write_integer(gpio_num);
 325         return 0;
 326 }
 327
 328 static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
 329 {
 330         /* Store (op (gpio_num), Local0) */
 331         acpigen_write_store();
 332         acpigen_soc_gpio_op(op, gpio_num);
 333         acpigen_emit_byte(LOCAL0_OP);
 334         return 0;
 335 }
 336
 337 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 338 {
 339         return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
 340 }
 341
 342 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 343 {
 344         return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
 345 }
 346
 347 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 348 {
 349         return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
 350 }
 351
 352 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 353 {
 354         return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
 355 }