src/soc/intel/icelake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <fsp/api.h>
   7 #include <fsp/util.h>
   8 #include <intelblocks/lpss.h>
   9 #include <intelblocks/xdci.h>
  10 #include <soc/intel/common/vbt.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/ramstage.h>
  13 #include <soc/soc_chip.h>
  14 #include <string.h>
  15 #include <intelblocks/mp_init.h>
  16 #include <fsp/ppi/mp_service_ppi.h>
  17
  18 static void parse_devicetree(FSP_S_CONFIG *params)
  19 {
  20         const struct soc_intel_icelake_config *config;
  21         config = config_of_soc();
  22
  23         for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
  24                 params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
  25
  26         for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
  27                 params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
  28                 params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
  29                 params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
  30         }
  31
  32         for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
  33                 params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
  34 }
  35
  36 static const pci_devfn_t serial_io_dev[] = {
  37         PCH_DEVFN_I2C0,
  38         PCH_DEVFN_I2C1,
  39         PCH_DEVFN_I2C2,
  40         PCH_DEVFN_I2C3,
  41         PCH_DEVFN_I2C4,
  42         PCH_DEVFN_I2C5,
  43         PCH_DEVFN_GSPI0,
  44         PCH_DEVFN_GSPI1,
  45         PCH_DEVFN_GSPI2,
  46         PCH_DEVFN_UART0,
  47         PCH_DEVFN_UART1,
  48         PCH_DEVFN_UART2
  49 };
  50
  51 /* UPD parameters to be initialized before SiliconInit */
  52 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
  53 {
  54         int i;
  55         FSP_S_CONFIG *params = &supd->FspsConfig;
  56
  57         struct device *dev;
  58         struct soc_intel_icelake_config *config;
  59         config = config_of_soc();
  60
  61         /* Parse device tree and enable/disable devices */
  62         parse_devicetree(params);
  63
  64         /* Load VBT before devicetree-specific config. */
  65         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
  66
  67         /* Set USB OC pin to 0 first */
  68         for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
  69                 params->Usb2OverCurrentPin[i] = 0;
  70
  71         for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
  72                 params->Usb3OverCurrentPin[i] = 0;
  73
  74         /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */
  75         params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
  76         /* TODO: Remove me as SkipMpInit is getting deprecated */
  77         params->SkipMpInit = 0;
  78
  79         mainboard_silicon_init_params(params);
  80
  81         dev = pcidev_path_on_root(SA_DEVFN_IGD);
  82         if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
  83                 params->PeiGraphicsPeimInit = 1;
  84         else
  85                 params->PeiGraphicsPeimInit = 0;
  86
  87         /* Unlock upper 8 bytes of RTC RAM */
  88         params->PchLockDownRtcMemoryLock = 0;
  89
  90         params->CnviBtAudioOffload = config->CnviBtAudioOffload;
  91         /* SATA */
  92         dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
  93         if (!dev)
  94                 params->SataEnable = 0;
  95         else {
  96                 params->SataEnable = dev->enabled;
  97                 params->SataMode = config->SataMode;
  98                 params->SataSalpSupport = config->SataSalpSupport;
  99                 memcpy(params->SataPortsEnable, config->SataPortsEnable,
 100                                 sizeof(params->SataPortsEnable));
 101                 memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
 102                                 sizeof(params->SataPortsDevSlp));
 103         }
 104
 105         /* Lan */
 106         dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
 107         if (!dev)
 108                 params->PchLanEnable = 0;
 109         else
 110                 params->PchLanEnable = dev->enabled;
 111
 112         /* Audio */
 113         params->PchHdaDspEnable = config->PchHdaDspEnable;
 114         params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
 115         params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
 116         params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
 117         params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
 118         params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
 119         params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
 120         params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
 121         params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
 122         params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
 123         params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
 124
 125         /* disable Legacy PME */
 126         memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
 127
 128         /* Legacy 8254 timer support */
 129         params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
 130         params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
 131
 132         /* S0ix */
 133         params->PchPmSlpS0Enable = config->s0ix_enable;
 134
 135         /* USB */
 136         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 137                 params->PortUsb20Enable[i] =
 138                         config->usb2_ports[i].enable;
 139                 params->Usb2OverCurrentPin[i] =
 140                         config->usb2_ports[i].ocpin;
 141                 params->Usb2PhyPetxiset[i] =
 142                         config->usb2_ports[i].pre_emp_bias;
 143                 params->Usb2PhyTxiset[i] =
 144                         config->usb2_ports[i].tx_bias;
 145                 params->Usb2PhyPredeemp[i] =
 146                         config->usb2_ports[i].tx_emp_enable;
 147                 params->Usb2PhyPehalfbit[i] =
 148                         config->usb2_ports[i].pre_emp_bit;
 149         }
 150
 151         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 152                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 153                 params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 154                 if (config->usb3_ports[i].tx_de_emp) {
 155                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 156                         params->Usb3HsioTxDeEmph[i] =
 157                                 config->usb3_ports[i].tx_de_emp;
 158                 }
 159                 if (config->usb3_ports[i].tx_downscale_amp) {
 160                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 161                         params->Usb3HsioTxDownscaleAmp[i] =
 162                                 config->usb3_ports[i].tx_downscale_amp;
 163                 }
 164         }
 165
 166         /* Enable xDCI controller if enabled in devicetree and allowed */
 167         dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
 168         if (!xdci_can_enable())
 169                 dev->enabled = 0;
 170         params->XdciEnable = dev->enabled;
 171
 172         /* PCI Express */
 173         for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
 174                 if (config->PcieClkSrcUsage[i] == 0)
 175                         config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
 176         }
 177         memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
 178                sizeof(config->PcieClkSrcUsage));
 179         memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
 180                sizeof(config->PcieClkSrcClkReq));
 181
 182         /* eMMC */
 183         dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0);
 184         if (!dev)
 185                 params->ScsEmmcEnabled = 0;
 186         else {
 187                 params->ScsEmmcEnabled = dev->enabled;
 188                 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 189                 params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
 190                 if (config->EmmcUseCustomDlls == 1) {
 191                         params->EmmcTxCmdDelayRegValue =
 192                                         config->EmmcTxCmdDelayRegValue;
 193                         params->EmmcTxDataDelay1RegValue =
 194                                         config->EmmcTxDataDelay1RegValue;
 195                         params->EmmcTxDataDelay2RegValue =
 196                                         config->EmmcTxDataDelay2RegValue;
 197                         params->EmmcRxCmdDataDelay1RegValue =
 198                                         config->EmmcRxCmdDataDelay1RegValue;
 199                         params->EmmcRxCmdDataDelay2RegValue =
 200                                         config->EmmcRxCmdDataDelay2RegValue;
 201                         params->EmmcRxStrobeDelayRegValue =
 202                                         config->EmmcRxStrobeDelayRegValue;
 203                 }
 204         }
 205
 206         /* SD */
 207         dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5);
 208         if (!dev)
 209                 params->ScsSdCardEnabled = 0;
 210         else {
 211                 params->ScsSdCardEnabled = dev->enabled;
 212                 params->SdCardPowerEnableActiveHigh =
 213                                 config->SdCardPowerEnableActiveHigh;
 214         }
 215
 216         params->Heci3Enabled = config->Heci3Enabled;
 217         params->Device4Enable = config->Device4Enable;
 218 }
 219
 220 /* Mainboard GPIO Configuration */
 221 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 222 {
 223         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 224 }
 225
 226 /* Return list of SOC LPSS controllers */
 227 const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
 228 {
 229         *size = ARRAY_SIZE(serial_io_dev);
 230         return serial_io_dev;
 231 }