src/soc/intel/apollolake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <bootstate.h>
   5 #include <cbmem.h>
   6 #include <console/console.h>
   7 #include <cpu/x86/mp.h>
   8 #include <device/mmio.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pci_ops.h>
  12 #include <intelblocks/acpi.h>
  13 #include <intelblocks/cfg.h>
  14 #include <intelblocks/fast_spi.h>
  15 #include <intelblocks/msr.h>
  16 #include <intelblocks/p2sb.h>
  17 #include <intelblocks/power_limit.h>
  18 #include <intelblocks/xdci.h>
  19 #include <fsp/api.h>
  20 #include <fsp/util.h>
  21 #include <intelblocks/cpulib.h>
  22 #include <intelblocks/itss.h>
  23 #include <intelblocks/pmclib.h>
  24 #include <romstage_handoff.h>
  25 #include <soc/cpu.h>
  26 #include <soc/heci.h>
  27 #include <soc/intel/common/vbt.h>
  28 #include <soc/iomap.h>
  29 #include <soc/itss.h>
  30 #include <soc/nvs.h>
  31 #include <soc/pci_devs.h>
  32 #include <soc/pm.h>
  33 #include <soc/systemagent.h>
  34 #include <spi-generic.h>
  35 #include <timer.h>
  36 #include <soc/ramstage.h>
  37 #include <soc/soc_chip.h>
  38
  39 #include "chip.h"
  40
  41 #define DUAL_ROLE_CFG0          0x80d8
  42 #define SW_VBUS_VALID_MASK      (1 << 24)
  43 #define SW_IDPIN_EN_MASK        (1 << 21)
  44 #define SW_IDPIN_MASK           (1 << 20)
  45 #define SW_IDPIN_HOST           (0 << 20)
  46 #define DUAL_ROLE_CFG1          0x80dc
  47 #define DRD_MODE_MASK           (1 << 29)
  48 #define DRD_MODE_HOST           (1 << 29)
  49
  50 #define CFG_XHCLKGTEN           0x8650
  51 /* Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown */
  52 #define NUEFBCGPS               (1 << 28)
  53 /* SRAM Power Gate Enable */
  54 #define SRAMPGTEN               (1 << 27)
  55 /* SS Link PLL Shutdown Enable */
  56 #define SSLSE                   (1 << 26)
  57 /* USB2 PLL Shutdown Enable */
  58 #define USB2PLLSE               (1 << 25)
  59 /* IOSF Sideband Trunk Clock Gating Enable */
  60 #define IOSFSTCGE               (1 << 24)
  61 /* BIT[23:20] HS Backbone PXP Trunk Clock Gate Enable */
  62 #define HSTCGE                  (1 << 23 | 1 << 22)
  63 /* BIT[19:16] SS Backbone PXP Trunk Clock Gate Enable */
  64 #define SSTCGE                  (1 << 19 | 1 << 18 | 1 << 17)
  65 /* XHC Ignore_EU3S */
  66 #define XHCIGEU3S               (1 << 15)
  67 /* XHC Frame Timer Clock Shutdown Enable */
  68 #define XHCFTCLKSE              (1 << 14)
  69 /* XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP */
  70 #define XHCBBTCGIPISO           (1 << 13)
  71 /* XHC HS Backbone PXP Trunk Clock Gate U2 non RWE */
  72 #define XHCHSTCGU2NRWE          (1 << 12)
  73 /* BIT[11:10] XHC USB2 PLL Shutdown Lx Enable */
  74 #define XHCUSB2PLLSDLE          (1 << 11 | 1 << 10)
  75 /* BIT[9:8] HS Backbone PXP PLL Shutdown Ux Enable */
  76 #define HSUXDMIPLLSE            (1 << 9)
  77 /* BIT[7:5] SS Backbone PXP PLL shutdown Ux Enable */
  78 #define SSPLLSUE                (1 << 6)
  79 /* XHC Backbone Local Clock Gating Enable */
  80 #define XHCBLCGE                (1 << 4)
  81 /* HS Link Trunk Clock Gating Enable */
  82 #define HSLTCGE                 (1 << 3)
  83 /* SS Link Trunk Clock Gating Enable */
  84 #define SSLTCGE                 (1 << 2)
  85 /* IOSF Backbone Trunk Clock Gating Enable */
  86 #define IOSFBTCGE               (1 << 1)
  87 /* IOSF Gasket Backbone Local Clock Gating Enable */
  88 #define IOSFGBLCGE              (1 << 0)
  89
  90 #define CFG_XHCPMCTRL           0x80a4
  91 /* BIT[7:4] LFPS periodic sampling for USB3 Ports */
  92 #define LFPS_PM_DISABLE_MASK    0xFFFFFF0F
  93
  94 const char *soc_acpi_name(const struct device *dev)
  95 {
  96         if (dev->path.type == DEVICE_PATH_DOMAIN)
  97                 return "PCI0";
  98
  99         if (dev->path.type == DEVICE_PATH_USB) {
 100                 switch (dev->path.usb.port_type) {
 101                 case 0:
 102                         /* Root Hub */
 103                         return "RHUB";
 104                 case 2:
 105                         /* USB2 ports */
 106                         switch (dev->path.usb.port_id) {
 107                         case 0: return "HS01";
 108                         case 1: return "HS02";
 109                         case 2: return "HS03";
 110                         case 3: return "HS04";
 111                         case 4: return "HS05";
 112                         case 5: return "HS06";
 113                         case 6: return "HS07";
 114                         case 7: return "HS08";
 115                         case 8:
 116                                 if (CONFIG(SOC_INTEL_GLK))
 117                                         return "HS09";
 118                         }
 119                         break;
 120                 case 3:
 121                         /* USB3 ports */
 122                         switch (dev->path.usb.port_id) {
 123                         case 0: return "SS01";
 124                         case 1: return "SS02";
 125                         case 2: return "SS03";
 126                         case 3: return "SS04";
 127                         case 4: return "SS05";
 128                         case 5: return "SS06";
 129                         }
 130                         break;
 131                 }
 132                 return NULL;
 133         }
 134
 135         if (dev->path.type != DEVICE_PATH_PCI)
 136                 return NULL;
 137
 138         switch (dev->path.pci.devfn) {
 139         /* DSDT: acpi/northbridge.asl */
 140         case SA_DEVFN_ROOT:
 141                 return "MCHC";
 142         /* DSDT: acpi/lpc.asl */
 143         case PCH_DEVFN_LPC:
 144                 return "LPCB";
 145         /* DSDT: acpi/xhci.asl */
 146         case PCH_DEVFN_XHCI:
 147                 return "XHCI";
 148         /* DSDT: acpi/pch_hda.asl */
 149         case PCH_DEVFN_HDA:
 150                 return "HDAS";
 151         /* DSDT: acpi/lpss.asl */
 152         case PCH_DEVFN_UART0:
 153                 return "URT1";
 154         case PCH_DEVFN_UART1:
 155                 return "URT2";
 156         case PCH_DEVFN_UART2:
 157                 return "URT3";
 158         case PCH_DEVFN_UART3:
 159                 return "URT4";
 160         case PCH_DEVFN_SPI0:
 161                 return "SPI1";
 162         case PCH_DEVFN_SPI1:
 163                 return "SPI2";
 164         case PCH_DEVFN_SPI2:
 165                 return "SPI3";
 166         case PCH_DEVFN_PWM:
 167                 return "PWM";
 168         case PCH_DEVFN_I2C0:
 169                 return "I2C0";
 170         case PCH_DEVFN_I2C1:
 171                 return "I2C1";
 172         case PCH_DEVFN_I2C2:
 173                 return "I2C2";
 174         case PCH_DEVFN_I2C3:
 175                 return "I2C3";
 176         case PCH_DEVFN_I2C4:
 177                 return "I2C4";
 178         case PCH_DEVFN_I2C5:
 179                 return "I2C5";
 180         case PCH_DEVFN_I2C6:
 181                 return "I2C6";
 182         case PCH_DEVFN_I2C7:
 183                 return "I2C7";
 184         /* Storage */
 185         case PCH_DEVFN_SDCARD:
 186                 return "SDCD";
 187         case PCH_DEVFN_EMMC:
 188                 return "EMMC";
 189         case PCH_DEVFN_SDIO:
 190                 return "SDIO";
 191         /* PCIe */
 192         case PCH_DEVFN_PCIE1:
 193                 return "RP03";
 194         case PCH_DEVFN_PCIE5:
 195                 return "RP01";
 196         }
 197
 198         return NULL;
 199 }
 200
 201 static struct device_operations pci_domain_ops = {
 202         .read_resources = pci_domain_read_resources,
 203         .set_resources = pci_domain_set_resources,
 204         .scan_bus = pci_domain_scan_bus,
 205         .acpi_name = &soc_acpi_name,
 206 };
 207
 208 static struct device_operations cpu_bus_ops = {
 209         .read_resources = noop_read_resources,
 210         .set_resources = noop_set_resources,
 211         .init = apollolake_init_cpus,
 212         .acpi_fill_ssdt = generate_cpu_entries,
 213 };
 214
 215 static void enable_dev(struct device *dev)
 216 {
 217         /* Set the operations if it is a special bus type */
 218         if (dev->path.type == DEVICE_PATH_DOMAIN)
 219                 dev->ops = &pci_domain_ops;
 220         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 221                 dev->ops = &cpu_bus_ops;
 222 }
 223
 224 /*
 225  * If the PCIe root port at function 0 is disabled,
 226  * the PCIe root ports might be coalesced after FSP silicon init.
 227  * The below function will swap the devfn of the first enabled device
 228  * in devicetree and function 0 resides a pci device
 229  * so that it won't confuse coreboot.
 230  */
 231 static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
 232 {
 233         struct device *func0;
 234         unsigned int devfn;
 235         int i;
 236         unsigned int inc = PCI_DEVFN(0, 1);
 237
 238         func0 = pcidev_path_on_root(devfn0);
 239         if (func0 == NULL)
 240                 return;
 241
 242         /* No more functions if function 0 is disabled. */
 243         if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff)
 244                 return;
 245
 246         devfn = devfn0 + inc;
 247
 248         /*
 249          * Increase function by 1.
 250          * Then find first enabled device to replace func0
 251          * as that port was move to func0.
 252          */
 253         for (i = 1; i < num_funcs; i++, devfn += inc) {
 254                 struct device *dev = pcidev_path_on_root(devfn);
 255                 if (dev == NULL)
 256                         continue;
 257
 258                 if (!dev->enabled)
 259                         continue;
 260                 /* Found the first enabled device in given dev number */
 261                 func0->path.pci.devfn = dev->path.pci.devfn;
 262                 dev->path.pci.devfn = devfn0;
 263                 break;
 264         }
 265 }
 266
 267 static void pcie_override_devicetree_after_silicon_init(void)
 268 {
 269         pcie_update_device_tree(PCH_DEVFN_PCIE1, 4);
 270         pcie_update_device_tree(PCH_DEVFN_PCIE5, 2);
 271 }
 272
 273 /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */
 274 static void set_sci_irq(void)
 275 {
 276         struct soc_intel_apollolake_config *cfg;
 277         uint32_t scis;
 278
 279         cfg = config_of_soc();
 280
 281         /* Change only if a device tree entry exists. */
 282         if (cfg->sci_irq) {
 283                 scis = soc_read_sci_irq_select();
 284                 scis &= ~SCI_IRQ_SEL;
 285                 scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL;
 286                 soc_write_sci_irq_select(scis);
 287         }
 288 }
 289
 290 static void soc_init(void *data)
 291 {
 292         struct soc_power_limits_config *soc_config;
 293         config_t *config;
 294
 295         /* Snapshot the current GPIO IRQ polarities. FSP is setting a
 296          * default policy that doesn't honor boards' requirements. */
 297         itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 298
 299         /*
 300          * Clear the GPI interrupt status and enable registers. These
 301          * registers do not get reset to default state when booting from S5.
 302          */
 303         gpi_clear_int_cfg();
 304
 305         fsp_silicon_init(romstage_handoff_is_resume());
 306
 307         /* Restore GPIO IRQ polarities back to previous settings. */
 308         itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 309
 310         /* override 'enabled' setting in device tree if needed */
 311         pcie_override_devicetree_after_silicon_init();
 312
 313         /*
 314          * Keep the P2SB device visible so it and the other devices are
 315          * visible in coreboot for driver support and PCI resource allocation.
 316          * There is a UPD setting for this, but it's more consistent to use
 317          * hide and unhide symmetrically.
 318          */
 319         p2sb_unhide();
 320
 321         /* Allocate ACPI NVS in CBMEM */
 322         cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
 323
 324         if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 325                 printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
 326         } else {
 327                 config = config_of_soc();
 328                 /* Set RAPL MSR for Package power limits */
 329                 soc_config = &config->power_limits_config;
 330                 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 331         }
 332
 333         /*
 334         * FSP-S routes SCI to IRQ 9. With the help of this function you can
 335         * select another IRQ for SCI.
 336         */
 337         set_sci_irq();
 338 }
 339
 340 static void soc_final(void *data)
 341 {
 342         /* Make sure payload/OS can't trigger global reset */
 343         pmc_global_reset_disable_and_lock();
 344 }
 345
 346 static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
 347 {
 348         switch (dev->path.pci.devfn) {
 349         case PCH_DEVFN_NPK:
 350                 /*
 351                  * Disable this device in the parse_devicetree_setting() function
 352                  * in romstage.c
 353                  */
 354                 break;
 355         case PCH_DEVFN_ISH:
 356                 silconfig->IshEnable = 0;
 357                 break;
 358         case PCH_DEVFN_SATA:
 359                 silconfig->EnableSata = 0;
 360                 break;
 361         case PCH_DEVFN_PCIE5:
 362                 silconfig->PcieRootPortEn[0] = 0;
 363                 silconfig->PcieRpHotPlug[0] = 0;
 364                 break;
 365         case PCH_DEVFN_PCIE6:
 366                 silconfig->PcieRootPortEn[1] = 0;
 367                 silconfig->PcieRpHotPlug[1] = 0;
 368                 break;
 369         case PCH_DEVFN_PCIE1:
 370                 silconfig->PcieRootPortEn[2] = 0;
 371                 silconfig->PcieRpHotPlug[2] = 0;
 372                 break;
 373         case PCH_DEVFN_PCIE2:
 374                 silconfig->PcieRootPortEn[3] = 0;
 375                 silconfig->PcieRpHotPlug[3] = 0;
 376                 break;
 377         case PCH_DEVFN_PCIE3:
 378                 silconfig->PcieRootPortEn[4] = 0;
 379                 silconfig->PcieRpHotPlug[4] = 0;
 380                 break;
 381         case PCH_DEVFN_PCIE4:
 382                 silconfig->PcieRootPortEn[5] = 0;
 383                 silconfig->PcieRpHotPlug[5] = 0;
 384                 break;
 385         case PCH_DEVFN_XHCI:
 386                 silconfig->Usb30Mode = 0;
 387                 break;
 388         case PCH_DEVFN_XDCI:
 389                 silconfig->UsbOtg = 0;
 390                 break;
 391         case PCH_DEVFN_I2C0:
 392                 silconfig->I2c0Enable = 0;
 393                 break;
 394         case PCH_DEVFN_I2C1:
 395                 silconfig->I2c1Enable = 0;
 396                 break;
 397         case PCH_DEVFN_I2C2:
 398                 silconfig->I2c2Enable = 0;
 399                 break;
 400         case PCH_DEVFN_I2C3:
 401                 silconfig->I2c3Enable = 0;
 402                 break;
 403         case PCH_DEVFN_I2C4:
 404                 silconfig->I2c4Enable = 0;
 405                 break;
 406         case PCH_DEVFN_I2C5:
 407                 silconfig->I2c5Enable = 0;
 408                 break;
 409         case PCH_DEVFN_I2C6:
 410                 silconfig->I2c6Enable = 0;
 411                 break;
 412         case PCH_DEVFN_I2C7:
 413                 silconfig->I2c7Enable = 0;
 414                 break;
 415         case PCH_DEVFN_UART0:
 416                 silconfig->Hsuart0Enable = 0;
 417                 break;
 418         case PCH_DEVFN_UART1:
 419                 silconfig->Hsuart1Enable = 0;
 420                 break;
 421         case PCH_DEVFN_UART2:
 422                 silconfig->Hsuart2Enable = 0;
 423                 break;
 424         case PCH_DEVFN_UART3:
 425                 silconfig->Hsuart3Enable = 0;
 426                 break;
 427         case PCH_DEVFN_SPI0:
 428                 silconfig->Spi0Enable = 0;
 429                 break;
 430         case PCH_DEVFN_SPI1:
 431                 silconfig->Spi1Enable = 0;
 432                 break;
 433         case PCH_DEVFN_SPI2:
 434                 silconfig->Spi2Enable = 0;
 435                 break;
 436         case PCH_DEVFN_SDCARD:
 437                 silconfig->SdcardEnabled = 0;
 438                 break;
 439         case PCH_DEVFN_EMMC:
 440                 silconfig->eMMCEnabled = 0;
 441                 break;
 442         case PCH_DEVFN_SDIO:
 443                 silconfig->SdioEnabled = 0;
 444                 break;
 445         case PCH_DEVFN_SMBUS:
 446                 silconfig->SmbusEnable = 0;
 447                 break;
 448 #if !CONFIG(SOC_INTEL_GLK)
 449         case SA_DEVFN_IPU:
 450                 silconfig->IpuEn = 0;
 451                 break;
 452 #endif
 453         case PCH_DEVFN_HDA:
 454                 silconfig->HdaEnable = 0;
 455                 break;
 456         default:
 457                 printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n",
 458                         PCI_SLOT(dev->path.pci.devfn),
 459                         PCI_FUNC(dev->path.pci.devfn));
 460                 break;
 461         }
 462 }
 463
 464 static void parse_devicetree(FSP_S_CONFIG *silconfig)
 465 {
 466         struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 467
 468         if (!dev) {
 469                 printk(BIOS_ERR, "Could not find root device\n");
 470                 return;
 471         }
 472         /* Only disable bus 0 devices. */
 473         for (dev = dev->bus->children; dev; dev = dev->sibling) {
 474                 if (!dev->enabled)
 475                         disable_dev(dev, silconfig);
 476         }
 477 }
 478
 479 static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
 480         *cfg, FSP_S_CONFIG *silconfig)
 481 {
 482 #if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these fields in FspsUpd.h yet */
 483         uint8_t port;
 484
 485         for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
 486                 if (cfg->usb_config_override) {
 487                         if (!cfg->usb2_port[port].enable)
 488                                 continue;
 489
 490                         silconfig->PortUsb20Enable[port] = 1;
 491                         silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin;
 492                 }
 493
 494                 if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
 495                         silconfig->PortUsb20PerPortTxPeHalf[port] =
 496                                 cfg->usb2eye[port].Usb20PerPortTxPeHalf;
 497
 498                 if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
 499                         silconfig->PortUsb20PerPortPeTxiSet[port] =
 500                                 cfg->usb2eye[port].Usb20PerPortPeTxiSet;
 501
 502                 if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
 503                         silconfig->PortUsb20PerPortTxiSet[port] =
 504                                 cfg->usb2eye[port].Usb20PerPortTxiSet;
 505
 506                 if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
 507                         silconfig->PortUsb20HsSkewSel[port] =
 508                                 cfg->usb2eye[port].Usb20HsSkewSel;
 509
 510                 if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
 511                         silconfig->PortUsb20IUsbTxEmphasisEn[port] =
 512                                 cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
 513
 514                 if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
 515                         silconfig->PortUsb20PerPortRXISet[port] =
 516                                 cfg->usb2eye[port].Usb20PerPortRXISet;
 517
 518                 if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
 519                         silconfig->PortUsb20HsNpreDrvSel[port] =
 520                                 cfg->usb2eye[port].Usb20HsNpreDrvSel;
 521         }
 522
 523         if (cfg->usb_config_override) {
 524                 for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) {
 525                         if (!cfg->usb3_port[port].enable)
 526                                 continue;
 527
 528                         silconfig->PortUsb30Enable[port] = 1;
 529                         silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin;
 530                 }
 531         }
 532 #endif
 533 }
 534
 535 static void glk_fsp_silicon_init_params_cb(
 536         struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
 537 {
 538 #if CONFIG(SOC_INTEL_GLK)
 539         uint8_t port;
 540         struct device *dev;
 541
 542         for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
 543                 if (!cfg->usb2eye[port].Usb20OverrideEn)
 544                         continue;
 545
 546                 silconfig->Usb2AfePehalfbit[port] =
 547                         cfg->usb2eye[port].Usb20PerPortTxPeHalf;
 548                 silconfig->Usb2AfePetxiset[port] =
 549                         cfg->usb2eye[port].Usb20PerPortPeTxiSet;
 550                 silconfig->Usb2AfeTxiset[port] =
 551                         cfg->usb2eye[port].Usb20PerPortTxiSet;
 552                 silconfig->Usb2AfePredeemp[port] =
 553                         cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
 554         }
 555
 556         dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM);
 557         silconfig->Gmm = dev ? dev->enabled : 0;
 558
 559         /* On Geminilake, we need to override the default FSP PCIe de-emphasis
 560          * settings using the device tree settings. This is because PCIe
 561          * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection
 562          * requires de-emphasis disabled. If we make this change common to both
 563          * Apollolake and Geminilake, then we need to add mainboard device tree
 564          * de-emphasis settings of 1 to Apollolake systems.
 565          */
 566         memcpy(silconfig->PcieRpSelectableDeemphasis,
 567                 cfg->pcie_rp_deemphasis_enable,
 568                 sizeof(silconfig->PcieRpSelectableDeemphasis));
 569         /*
 570          * FSP does not know what the clock requirements are for the
 571          * device on SPI bus, hence it should not modify what coreboot
 572          * has set up. Hence skipping in FSP.
 573          */
 574         silconfig->SkipSpiPCP = 1;
 575
 576         /*
 577          * FSP provides UPD interface to execute IPC command. In order to
 578          * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
 579          * PMIC PCH_PWROK delay.
 580          */
 581         silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
 582
 583         /*
 584          * Options to disable XHCI Link Compliance Mode.
 585          */
 586         silconfig->DisableComplianceMode = cfg->DisableComplianceMode;
 587
 588         /*
 589          * Options to change USB3 ModPhy setting for Integrated Filter value.
 590          */
 591         silconfig->ModPhyIfValue = cfg->ModPhyIfValue;
 592
 593         /*
 594          * Options to bump USB3 LDO voltage with 40mv.
 595          */
 596         silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump;
 597
 598         /*
 599          * Options to adjust PMIC Vdd2 voltage.
 600          */
 601         silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage;
 602 #endif
 603 }
 604
 605 void __weak mainboard_devtree_update(struct device *dev)
 606 {
 607         /* Override dev tree settings per board */
 608 }
 609
 610 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 611 {
 612         FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
 613         struct soc_intel_apollolake_config *cfg;
 614         struct device *dev;
 615
 616         /* Load VBT before devicetree-specific config. */
 617         silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get();
 618
 619         dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 620         cfg = config_of(dev);
 621
 622         mainboard_devtree_update(dev);
 623
 624         /* Parse device tree and disable unused device*/
 625         parse_devicetree(silconfig);
 626
 627         memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
 628                sizeof(silconfig->PcieRpClkReqNumber));
 629
 630         memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
 631                sizeof(silconfig->PcieRpHotPlug));
 632
 633         switch (cfg->serirq_mode) {
 634         case SERIRQ_QUIET:
 635                 silconfig->SirqEnable = 1;
 636                 silconfig->SirqMode = 0;
 637                 break;
 638         case SERIRQ_CONTINUOUS:
 639                 silconfig->SirqEnable = 1;
 640                 silconfig->SirqMode = 1;
 641                 break;
 642         case SERIRQ_OFF:
 643         default:
 644                 silconfig->SirqEnable = 0;
 645                 break;
 646         }
 647
 648         if (cfg->emmc_tx_cmd_cntl != 0)
 649                 silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
 650         if (cfg->emmc_tx_data_cntl1 != 0)
 651                 silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
 652         if (cfg->emmc_tx_data_cntl2 != 0)
 653                 silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
 654         if (cfg->emmc_rx_cmd_data_cntl1 != 0)
 655                 silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
 656         if (cfg->emmc_rx_strobe_cntl != 0)
 657                 silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
 658         if (cfg->emmc_rx_cmd_data_cntl2 != 0)
 659                 silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
 660         if (cfg->emmc_host_max_speed != 0)
 661                 silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed;
 662
 663         silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
 664
 665         /* Disable monitor mwait since it is broken due to a hardware bug
 666          * without a fix. Specific to Apollolake.
 667          */
 668         if (!CONFIG(SOC_INTEL_GLK))
 669                 silconfig->MonitorMwaitEnable = 0;
 670
 671         silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
 672
 673         /* Disable setting of EISS bit in FSP. */
 674         silconfig->SpiEiss = 0;
 675
 676         /* Disable FSP from locking access to the RTC NVRAM */
 677         silconfig->RtcLock = 0;
 678
 679         /* Enable Audio clk gate and power gate */
 680         silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
 681         silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
 682         /* BIOS config lockdown Audio clk and power gate */
 683         silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
 684         if (CONFIG(SOC_INTEL_GLK))
 685                 glk_fsp_silicon_init_params_cb(cfg, silconfig);
 686         else
 687                 apl_fsp_silicon_init_params_cb(cfg, silconfig);
 688
 689         /* Enable xDCI controller if enabled in devicetree and allowed */
 690         dev = pcidev_path_on_root(PCH_DEVFN_XDCI);
 691         if (!xdci_can_enable())
 692                 dev->enabled = 0;
 693         silconfig->UsbOtg = dev->enabled;
 694
 695         /* Set VTD feature according to devicetree */
 696         silconfig->VtdEnable = cfg->enable_vtd;
 697
 698         dev = pcidev_path_on_root(SA_DEVFN_IGD);
 699         if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
 700                 silconfig->PeiGraphicsPeimInit = 1;
 701         else
 702                 silconfig->PeiGraphicsPeimInit = 0;
 703
 704         mainboard_silicon_init_params(silconfig);
 705 }
 706
 707 struct chip_operations soc_intel_apollolake_ops = {
 708         CHIP_NAME("Intel Apollolake SOC")
 709         .enable_dev = &enable_dev,
 710         .init = &soc_init,
 711         .final = &soc_final
 712 };
 713
 714 static void drop_privilege_all(void)
 715 {
 716         /* Drop privilege level on all the CPUs */
 717         if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL) < 0)
 718                 printk(BIOS_ERR, "failed to enable untrusted mode\n");
 719 }
 720
 721 static void configure_xhci_host_mode_port0(void)
 722 {
 723         uint32_t *cfg0;
 724         uint32_t *cfg1;
 725         const struct resource *res;
 726         uint32_t reg;
 727         struct stopwatch sw;
 728         struct device *xhci_dev = PCH_DEV_XHCI;
 729
 730         printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n");
 731         res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 732         cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
 733         cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
 734         reg = read32(cfg0);
 735         if (!(reg & SW_IDPIN_EN_MASK))
 736                 return;
 737
 738         reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK);
 739         write32(cfg0, reg);
 740
 741         stopwatch_init_msecs_expire(&sw, 10);
 742         /* Wait for the host mode status bit. */
 743         while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
 744                 if (stopwatch_expired(&sw)) {
 745                         printk(BIOS_ERR, "Timed out waiting for host mode.\n");
 746                         return;
 747                 }
 748         }
 749
 750         printk(BIOS_INFO, "xHCI port 0 host switch over took %lu ms\n",
 751                 stopwatch_duration_msecs(&sw));
 752 }
 753
 754 static int check_xdci_enable(void)
 755 {
 756         struct device *dev = PCH_DEV_XDCI;
 757
 758         return !!dev->enabled;
 759 }
 760
 761 static void disable_xhci_lfps_pm(void)
 762 {
 763         struct soc_intel_apollolake_config *cfg;
 764
 765         cfg = config_of_soc();
 766
 767         if (cfg->disable_xhci_lfps_pm) {
 768                 void *addr;
 769                 const struct resource *res;
 770                 uint32_t reg;
 771                 struct device *xhci_dev = PCH_DEV_XHCI;
 772
 773                 res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 774                 addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL);
 775                 reg = read32(addr);
 776                 printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg);
 777                 if (reg) {
 778                         reg &= LFPS_PM_DISABLE_MASK;
 779                         write32(addr, reg);
 780                         printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n");
 781                 }
 782         }
 783 }
 784
 785 void platform_fsp_notify_status(enum fsp_notify_phase phase)
 786 {
 787         if (phase == END_OF_FIRMWARE) {
 788
 789                 /*
 790                  * Before hiding P2SB device and dropping privilege level,
 791                  * dump CSE status and disable HECI1 interface.
 792                  */
 793                 heci_cse_lockdown();
 794
 795                 /* Hide the P2SB device to align with previous behavior. */
 796                 p2sb_hide();
 797
 798                 /*
 799                  * As per guidelines BIOS is recommended to drop CPU privilege
 800                  * level to IA_UNTRUSTED. After that certain device registers
 801                  * and MSRs become inaccessible supposedly increasing system
 802                  * security.
 803                  */
 804                 drop_privilege_all();
 805
 806                 /*
 807                  * When USB OTG is set, GLK FSP enables xHCI SW ID pin and
 808                  * configures USB-C as device mode. Force USB-C into host mode.
 809                  */
 810                 if (check_xdci_enable())
 811                         configure_xhci_host_mode_port0();
 812
 813                 /*
 814                  * Override GLK xhci clock gating register(XHCLKGTEN) to
 815                  * mitigate USB device suspend and resume failure.
 816                  */
 817                 if (CONFIG(SOC_INTEL_GLK)) {
 818                         uint32_t *cfg;
 819                         const struct resource *res;
 820                         uint32_t reg;
 821                         struct device *xhci_dev = PCH_DEV_XHCI;
 822
 823                         res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 824                         cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN);
 825                         reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE |
 826                                 HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE |
 827                                 XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE |
 828                                 XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE |
 829                                 IOSFGBLCGE;
 830                         write32(cfg, reg);
 831                 }
 832
 833                 /* Disable XHCI LFPS power management if the option in dev tree is set. */
 834                 disable_xhci_lfps_pm();
 835         }
 836 }
 837
 838 /*
 839  * spi_flash init() needs to run unconditionally on every boot (including
 840  * resume) to allow write protect to be disabled for eventlog and nvram
 841  * updates. This needs to be done as early as possible in ramstage. Thus, add a
 842  * callback for entry into BS_PRE_DEVICE.
 843  */
 844 static void spi_flash_init_cb(void *unused)
 845 {
 846         fast_spi_init();
 847 }
 848
 849 __weak
 850 void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 851 {
 852         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 853 }
 854
 855 /* Handle FSP logo params */
 856 const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
 857 {
 858         return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
 859 }
 860
 861 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);