src/soc/mediatek/common/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <bootmode.h>
   5 #include <cbfs.h>
   6 #include <console/console.h>
   7 #include <ip_checksum.h>
   8 #include <mrc_cache.h>
   9 #include <soc/dramc_param.h>
  10 #include <soc/emi.h>
  11 #include <soc/mmu_operations.h>
  12 #include <symbols.h>
  13 #include <timer.h>
  14
  15 /* This must be defined in chromeos.fmd in same name and size. */
  16 #define CALIBRATION_REGION              "RW_MRC_CACHE"
  17 #define CALIBRATION_REGION_SIZE         0x2000
  18
  19 _Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
  20                "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
  21
  22 const char *get_dram_geometry_str(u32 ddr_geometry);
  23 const char *get_dram_type_str(u32 ddr_type);
  24
  25 static int mt_mem_test(const struct dramc_data *dparam)
  26 {
  27         if (CONFIG(MEMORY_TEST)) {
  28                 u8 *addr = _dram;
  29                 const struct ddr_base_info *ddr_info = &dparam->ddr_info;
  30
  31                 for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) {
  32                         int result = complex_mem_test(addr, 0x2000);
  33
  34                         if (result != 0) {
  35                                 printk(BIOS_ERR,
  36                                        "[MEM] complex R/W mem test failed: %d\n", result);
  37                                 return -1;
  38                         }
  39                         printk(BIOS_DEBUG, "[MEM] rank %u complex R/W mem test passed\n", rank);
  40
  41                         addr += ddr_info->rank_size[rank];
  42                 }
  43         }
  44
  45         return 0;
  46 }
  47
  48 const char *get_dram_geometry_str(u32 ddr_geometry)
  49 {
  50         const char *s;
  51
  52         switch (ddr_geometry) {
  53         case DDR_TYPE_2CH_2RK_4GB_2_2:
  54                 s = "2CH_2RK_4GB_2_2";
  55                 break;
  56         case DDR_TYPE_2CH_2RK_6GB_3_3:
  57                 s = "2CH_2RK_6GB_3_3";
  58                 break;
  59         case DDR_TYPE_2CH_2RK_8GB_4_4:
  60                 s = "2CH_2RK_8GB_4_4";
  61                 break;
  62         case DDR_TYPE_2CH_2RK_8GB_4_4_BYTE:
  63                 s = "2CH_2RK_8GB_4_4_BYTE";
  64                 break;
  65         case DDR_TYPE_2CH_1RK_4GB_4_0:
  66                 s = "2CH_1RK_4GB_4_0";
  67                 break;
  68         case DDR_TYPE_2CH_2RK_6GB_2_4:
  69                 s = "2CH_2RK_6GB_2_4";
  70                 break;
  71         default:
  72                 s = "";
  73                 break;
  74         }
  75
  76         return s;
  77 }
  78
  79 const char *get_dram_type_str(u32 ddr_type)
  80 {
  81         const char *s;
  82
  83         switch (ddr_type) {
  84         case DDR_TYPE_DISCRETE:
  85                 s = "DSC";
  86                 break;
  87         case DDR_TYPE_EMCP:
  88                 s = "EMCP";
  89                 break;
  90         default:
  91                 s = "";
  92                 break;
  93         }
  94
  95         return s;
  96 }
  97
  98 static int dram_run_fast_calibration(struct dramc_param *dparam)
  99 {
 100         const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS;
 101         if (dparam->dramc_datas.ddr_info.config_dvfs != config) {
 102                 printk(BIOS_WARNING,
 103                        "DRAM-K: Incompatible config for calibration data from flash "
 104                        "(expected: %#x, saved: %#x)\n",
 105                        config, dparam->dramc_datas.ddr_info.config_dvfs);
 106                 return -1;
 107         }
 108
 109         printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n");
 110         init_dram_by_params(dparam);
 111         if (mt_mem_test(&dparam->dramc_datas) == 0)
 112                 return 0;
 113
 114         return DRAMC_ERR_FAST_CALIBRATION;
 115 }
 116
 117 static int dram_run_full_calibration(struct dramc_param *dparam)
 118 {
 119         /* Load and run the provided blob for full-calibration if available */
 120         struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram");
 121
 122         initialize_dramc_param(dparam);
 123         dump_param_header(dparam);
 124
 125         if (cbfs_prog_stage_load(&dram)) {
 126                 printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n");
 127                 return -2;
 128         }
 129
 130         dparam->do_putc = do_putchar;
 131
 132         prog_set_entry(&dram, prog_entry(&dram), dparam);
 133         prog_run(&dram);
 134         if (dparam->header.status != DRAMC_SUCCESS) {
 135                 printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n",
 136                        dparam->header.status);
 137                 return -3;
 138         }
 139
 140         if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) {
 141                 printk(BIOS_ERR,
 142                        "DRAM-K: Full calibration executed without saving parameters. "
 143                        "Please ensure the blob is built properly.\n");
 144                 return -4;
 145         }
 146
 147         return 0;
 148 }
 149
 150 static void mem_init_set_default_config(struct dramc_param *dparam,
 151                                         const struct sdram_info *dram_info)
 152 {
 153         u32 type, geometry;
 154         memset(dparam, 0, sizeof(*dparam));
 155
 156         type = dram_info->ddr_type;
 157         geometry = dram_info->ddr_geometry;
 158
 159         dparam->dramc_datas.ddr_info.sdram.ddr_type = type;
 160
 161         if (CONFIG(MEDIATEK_DRAM_DVFS))
 162                 dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS;
 163
 164         dparam->dramc_datas.ddr_info.sdram.ddr_geometry = geometry;
 165
 166         printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n",
 167                get_dram_type_str(type),
 168                dparam->dramc_datas.ddr_info.config_dvfs,
 169                get_dram_geometry_str(geometry));
 170 }
 171
 172 static void mt_mem_init_run(struct dramc_param *dparam,
 173                             const struct sdram_info *dram_info)
 174 {
 175         const ssize_t mrc_cache_size = sizeof(dparam->dramc_datas);
 176         ssize_t data_size;
 177         struct stopwatch sw;
 178         int ret;
 179
 180         /* Load calibration params from flash and run fast calibration */
 181         mem_init_set_default_config(dparam, dram_info);
 182         data_size = mrc_cache_load_current(MRC_TRAINING_DATA,
 183                                            DRAMC_PARAM_HEADER_VERSION,
 184                                            &dparam->dramc_datas,
 185                                            mrc_cache_size);
 186         if (data_size == mrc_cache_size) {
 187                 printk(BIOS_INFO, "DRAM-K: Running fast calibration\n");
 188                 stopwatch_init(&sw);
 189
 190                 ret = dram_run_fast_calibration(dparam);
 191                 if (ret != 0) {
 192                         printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration "
 193                                "in %ld msecs, error: %d\n",
 194                                stopwatch_duration_msecs(&sw), ret);
 195
 196                         /* Erase flash data after fast calibration failed */
 197                         memset(&dparam->dramc_datas, 0xa5, mrc_cache_size);
 198                         if (mrc_cache_stash_data(MRC_TRAINING_DATA,
 199                                                  DRAMC_PARAM_HEADER_VERSION,
 200                                                  &dparam->dramc_datas, mrc_cache_size))
 201                                 printk(BIOS_ERR, "DRAM-K: Failed to erase "
 202                                        "calibration data\n");
 203                 } else {
 204                         printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n",
 205                                stopwatch_duration_msecs(&sw));
 206                         return;
 207                 }
 208         } else {
 209                 printk(BIOS_WARNING, "DRAM-K: Invalid data in flash (size: %#zx, expected: %#zx)\n",
 210                        data_size, mrc_cache_size);
 211         }
 212
 213         /* Run full calibration */
 214         printk(BIOS_INFO, "DRAM-K: Running full calibration\n");
 215         mem_init_set_default_config(dparam, dram_info);
 216
 217         stopwatch_init(&sw);
 218         int err = dram_run_full_calibration(dparam);
 219         if (err == 0) {
 220                 printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n",
 221                        stopwatch_duration_msecs(&sw));
 222
 223                 if (mrc_cache_stash_data(MRC_TRAINING_DATA,
 224                                          DRAMC_PARAM_HEADER_VERSION,
 225                                          &dparam->dramc_datas, mrc_cache_size) == 0)
 226                         printk(BIOS_DEBUG, "DRAM-K: Calibration params saved "
 227                                "to flash: version=%#x, size=%#zx\n",
 228                                DRAMC_PARAM_HEADER_VERSION, sizeof(*dparam));
 229                 else
 230                         printk(BIOS_ERR, "DRAM-K: Failed to save calibration "
 231                                "data to flash\n");
 232         } else {
 233                 printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n",
 234                        stopwatch_duration_msecs(&sw));
 235         }
 236 }
 237
 238 void mt_mem_init(struct dramc_param *dparam)
 239 {
 240         const struct sdram_info *sdram_param = get_sdram_config();
 241
 242         mt_mem_init_run(dparam, sdram_param);
 243 }
 244
 245 void mtk_dram_init(void)
 246 {
 247         /* dramc_param is too large to fit in stack. */
 248         static struct dramc_param dramc_parameter;
 249         mt_mem_init(&dramc_parameter);
 250         mtk_mmu_after_dram();
 251 }